S6E2C5 Series
32-bit ARM
®
Cortex
®
-M4F
FM4 Microcontroller
Devices in the S6E2C5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This
series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as
motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I
2
C, LIN). The products that
are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part
(002-04856)."
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 200 MHz frequency operation
FPU built-in
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
embedded system
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
Up to 25-bit address bus
Maximum Access size: 256M byte
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble function
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4
Mbytes units.
Integrated nested vectored interrupt controller (NVIC): 1 NMI
(non-maskable interrupt) and 128 peripheral interrupts and
16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
Possible to set two kinds of the scramble key
Note: It is necessary to use the Cypress provided software
library to use the scramble function.
On-chip Memories
Flash memory
This series is based on two independent on-chip flash
memories.
to 2048 Kbytes
Built-in flash accelerator system with 16 Kbytes trace buffer
memory
Read access to flash memory that can be achieved without
wait-cycle up to an operating frequency of 72 MHz. Even at
the operating frequency more than 72 MHz, an equivalent
single cycle access to flash memory can be obtained by
the flash accelerator system.
Security function for code protection
Up
USB Interface (Max two Channels)
The USB interface is composed of a device and a host.
USB device
USB
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to system bus of Cortex-M4F core.
SRAM0:
2.0 Full-speed supported
Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can be selected bulk-transfer,
interrupt-transfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
• EndPoint 1 to 5 comprise double buffer
The size of each endpoint is as follows.
• Endpoint 0, 2 to 5: 64 byte
• EndPoint 1: 256 byte
USB host
USB2.0
up to 192 Kbytes
SRAM1: 32 Kbytes
SRAM2: 32 Kbytes
Full-Speed/Low-Speed supported
Bulk-transfer, interrupt-transfer, and isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 20, 2017
Cypress Semiconductor Corporation
Document Number: 002-04984 Rev.*B
•
198 Champion Court
S6E2C5 Series
CAN Interface (Max two Channels)
Compatible with CAN specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32-message buffer
I
2
C
mode (Max 100 kbps)/Fast mode (Max 400 kbps)
supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A
and ch 7 = ch B) supported
Standard
CAN-FD Interface (One Channel)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 5 Mbps
Message buffer for receiver: up to 192 messages
Message buffer for transmitter: up to 32 messages
CAN with flexible data rate (non-ISO CAN FD)
Notes:
CAN
DMA Controller (Eight channels)
DMA controller has an independent bus, so the CPU and
DMA controller can process simultaneously.
Eight independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 GB)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
FD cannot communicate between non-ISO CAN FD
and ISO CAN FD, because non-ISO CAN FD and ISO
CAN FD are different frame format.
About the problem of "non-ISO CAN FD", see the White
Paper from CiA(CAN in Automation).
http://www.can-newsletter.org/engineering/standardization/
141222_can-fd-and-crc-issued_white-paper_bosch
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Multi-function Serial Interface (Max 16 channels)
Separate 64 byte receive and transmit FIFO buffers for
channels 0 to 7.
DSTC (Descriptor System data Transfer Controller;
256 Channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the descriptor system and,
following the specified contents of the descriptor that has
already been constructed on the memory, can access directly
the memory/peripheral device and perform the data-transfer
operation.
It supports the software activation, the hardware activation,
and the chain activation functions.
Operation mode is selectable for each channel from the
following:
UART
CSIO (SPI)
LIN
I
2
C
UART
Full-duplex
Selection
double buffer
with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detect functions available (parity errors,
framing errors, and overrun errors)
A/D Converter (Max 32 channels)
12-bit A/D Converter
approximation type
Built-in three units
Conversion time: 0.5 μs at 5 V
Priority conversion available (priority at two levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for priority conversion: 4 steps)
Successive
CSIO (SPI)
Full-duplex
Built-in
double buffer
dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch 6 and ch 7 only)
Supports high-speed SPI (ch 4 and ch 6 only)
Data length 5 to 16-bit
LIN
LIN
protocol Rev.2.1 supported
Full-duplex double buffer
Master/slave mode supported
LIN break field generation (can change to 13- to 16-bit
length)
LIN break delimiter generation (can change to 1- to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Document Number: 002-04984 Rev.*B
D/A Converter (Max 2 Channels)
R-2R type
12-bit resolution
Page 2 of 201
S6E2C5 Series
Base Timer (Max 16 Channels)
Operation mode is selected from the following for each
channel:
Real-Time Clock (RTC)
The real-time clock can count year, month, day, hour, minute,
second, or day of the week from 00 to 99.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Interrupt function with specifying date and time
(year/month/day/hour/minute) is available. This function is
also available by specifying only year, month, day, hour, or
minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
General Purpose I/O Port
This series can use its pins as general purpose I/O ports
when they are not used for external bus or peripherals;
moreover, the port relocate function is built in. It can set the
I/O port to which the peripheral function can be allocated.
Quadrature Position/Revolution Counter (QPRC;
Max four Channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. It is also
possible to use up/down counter.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port-relocate function
Up to 120 high-speed general-purpose I/O ports in 144 pin
package
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Some pins 5V tolerant I/O.
See 4. Pin Descriptions and 5. I/O Circuit Type for the
corresponding pins.
Multi-function Timer (Max three Units)
The multi-function timer is composed of the following blocks:
Minimum resolution: 5.00 ns
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the following for each
channel:
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
Output compare × 6 ch/unit
A/D activation compare × 6 ch/unit
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
The following functions can be used to achieve the motor
control:
Free-running
Periodic (= Reload)
One shot
Watch Counter
The watch counter is used for wake up from low-power
consumption mode. It is possible to select the main clock,
sub clock, built-in High-speed CR clock, or built-in low-speed
CR clock as the clock source.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (motor emergency stop) interrupt function
Interval timer: up to 64 s (max) with a sub clock of 32.768
kHz
External Interrupt Controller Unit
External interrupt input pin: Max 32 pins
Include one non-maskable interrupt (NMI)
Document Number: 002-04984 Rev.*B
Page 3 of 201
S6E2C5 Series
Watchdog Timer (2 Channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs: a "hardware"
watchdog and a "software" watchdog.
The hardware watchdog timer is clocked by low-speed
internal CR oscillator. The hardware watchdog is thus active
in any power saving mode except RTC mode and Stop mode.
I
2
S (Inter-IC Sound Bus) Interface (TX x 1 channel,
RX x 1 channel)
Supports three transfer protocols
I
2
S
justified
mode
Separate clock generation block for flexible system
integration options
DSP
Left
Master/slave mode selectable
RX Only, TX Only or TX and RX simultaneous operation
selectable
Cyclic Redundancy Check (CRC) Accelerator
The CRC accelerator helps to verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Word length is programmable from 7-bits to 32 bits
RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66
words x 32-bits)
DMA, interrupts, or polling based data transfer supported
CCITT CRC16 generator polynomial: 0x1021
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
Clock and Reset
Clocks
Programmable Cyclic Redundancy Check
(PRGCRC) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16, IEEE-802.3 CRC32 and generating
polynomial are supported.
Five clock sources (two external oscillators, two internal CR
oscillators, and Main PLL) that are dynamically selectable.
clock: 4 MHz to 48 MHz
Sub clock: 32.768 kHz
High-speed internal CR clock: 4 MHz
Low-speed internal CR clock: 100 kHz
Main PLL Clock
Main
CCITT CRC16 generator polynomial: 0x1021
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
Generating polynomial
Resets
requests from INITX pin
Power on reset
Software reset
Watchdog timer reset
Low-voltage detector reset
Clock supervisor reset
Reset
SD Card Interface
It is possible to use the SD card that conforms to the
following standards.
Clock Supervisor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
1-bit or 4-bit data bus
Low-Voltage Detector (LVD)
This Series include two-stage monitoring of voltage on the
VCC pins. when the voltage falls below the voltage that has
been set, the low-voltage detector function generates an
interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-04984 Rev.*B
Page 4 of 201
S6E2C5 Series
Low-power Consumption Mode
Six low power consumption modes are supported.
Debug
Serial wire JTAG debug port (SWJ-DP)
Embedded trace macrocells (ETM) provide comprehensive
debug and trace facilities.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable from with/without RAM
retention)
AHB trace macrocells (HTM)
Unique ID
Unique value of the device (41-bit) is set.
Deep standby stop (selectable from with/without RAM
retention)
Power Supply
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral
functions not used.
Four power supplies
range voltage:
VCC
= 2.7 V to 5.5 V
Power supply for USB ch 0 I/O:
USBVCC0 = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for USB ch 1 I/O:
USBVCC1 = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for VBAT:
VBAT
= 1.65 V to 5.5 V
Wide
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32-kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Document Number: 002-04984 Rev.*B
Page 5 of 201
