S71NS128JA0/S71NS064JA0
Stacked Multi-Chip Product (MCP)
128 Megabit (8 M x 16-Bit) and 64 Megabit (4 M x 16-Bit),
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memories with
16 Megabit (1M x 16-Bit) pSRAM
Data Sheet
ADVANCE
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Publication Number
S71NS-JA0_00
Revision
A
Amendment
6
Issue Date
September 22, 2005
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
S71NS128JA0/S71NS064JA0
Stacked Multi-Chip Product (MCP)
128 Megabit (8 M x 16-Bit) and 64 Megabit (4 M x 16-Bit),
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Flash Memories with
16 Megabit (1M x 16-Bit) pSRAM
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
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Publication Number
S71NS-JA0_00
Revision
A
Amendment
6
Issue Date
September 22, 2005
A d v a n c e
I n f o r m a t i o n
Contents
Notice On Data Sheet Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Physical Dimensions–S71NS128JA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
NLA048—48-Ball
Very Thin Fine-Pitch Ball Grid Array (FBGA)
10 x 11
mm Package ...........................................10
NLB044—44-Ball
Very Thin Fine-Pitch Ball Grid Array (FBGA)
9.2 x 8
mm Package .......................................... 11
Device History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Appendix B: Daisy Chain Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
pSRAM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
pSRAM Device Bus Operations ............................................................................................................................................... 16
pSRAM DC Characteristics ...................................................................................................................................................... 16
pSRAM AC Characteristics ....................................................................................................................................................... 16
pSRAM Device Operation ......................................................................................................................................................... 17
pSRAM Read Access ................................................................................................................................................................... 17
pSRAM Write Access ................................................................................................................................................................. 17
Configuration Register Access ................................................................................................................................................. 17
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Tables
Table 1
Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
NLA048 Daisy Chain Layout (Top View, Balls Facing Down) .................................................................................................... 14
NLB044 Daisy Chain Layout (Top View, Balls Facing Down)..................................................................................................... 15
Configuration Register Read Access.................................................................................................................................................. 18
Configuration Register Write Access................................................................................................................................................. 18
pSRAM Read Cycle 1 (WE# = VIH)..................................................................................................................................................... 19
pSRAM Read Cycle 2 (WE# = VIH).................................................................................................................................................... 19
pSRAM Write Cycle 1 (OE# = VIH)................................................................................................................................................... 20
pSRAM Write Cycle 2 (OE# = VIH)................................................................................................................................................. 20
2
S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
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S71NS128JA0/S71NS064JA0
S71NS-JA0_00_A6 September 22, 2005