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S71NS64NA0BFWMW3

Memory Circuit, 4MX16, CMOS, PBGA44, 7.70 X 6.20 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-44

器件类别:存储    存储   

厂商名称:SPANSION

厂商官网:http://www.spansion.com/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
SPANSION
零件包装代码
BGA
包装说明
TFBGA,
针数
44
Reach Compliance Code
compli
其他特性
PSRAM IS ORGANIZED AS 1M X 16; SYNCHRONOUS BURST MODE ALSO POSSIBLE
JESD-30 代码
R-PBGA-B44
JESD-609代码
e1
长度
7.7 mm
内存密度
67108864 bi
内存集成电路类型
MEMORY CIRCUIT
内存宽度
16
湿度敏感等级
3
功能数量
1
端子数量
44
字数
4194304 words
字数代码
4000000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-25 °C
组织
4MX16
封装主体材料
PLASTIC/EPOXY
封装代码
TFBGA
封装形状
RECTANGULAR
封装形式
GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)
260
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
1.95 V
最小供电电压 (Vsup)
1.7 V
标称供电电压 (Vsup)
1.8 V
表面贴装
YES
技术
CMOS
温度等级
OTHER
端子面层
TIN SILVER COPPER
端子形式
BALL
端子节距
0.5 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
40
宽度
6.285 mm
文档预览
S71NS128NA0/S71NS064NA0 Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBit™ Flash Memory
and pSRAM 128 Mb (8M x 16-bit) and 64 Mb (4M x 16-Bit),
110 nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/
Write, Burst Mode Flash Memory with
16 Mb (1M x 16-Bit) pSRAM
Data Sheet
ADVANCE
INFORMATION
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Publication Number
S71NS128_064NA0_00
Revision
A
Amendment
1
Issue Date
September 23, 2005
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S71NS128NA0/S71NS064NA0 Based MCPs
S71NS128_064NA0_00_A1 September 23, 2005
S71NS128NA0/S71NS064NA0 Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBit™ Flash Memory
and pSRAM 128 Mb (8M x 16-bit) and 64 Mb (4M x 16-Bit),
110 nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/
Write, Burst Mode Flash Memory with 16 Mb (1M x 16-Bit)
pSRAM
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
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General Description
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Publication Number
S71NS128_064NA0_00
Revision
A
Amendment
1
Issue Date
September 23, 2005
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A d v a n c e
I n f o r m a t i o n
Contents
S71NS128NA0/S71NS064NA0 Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
S71NS128NA0, 44-ball Very-Thin FBGA (NLB044) Pinout, NS128N + 16 PSRAM................................................................9
S71NS064NA0, 44-ball Very-Thin FBGA (NLD044) Pinout, NS064N + 16 PSRAM .......................................................... 10
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Order Number .........................................................................................................................................................................................12
Physical Dimension — S71NS128NA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
NLB044, 44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package .......................................................13
Physical Dimension — S71NS064NA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
NLD044, 44-Ball Very Thin Fine-pitch Ball Grid Array (BGA) 7.7 x 6.2 mm....................................................................... 14
S29NSxxxN MirrorBit
TM
Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VersatileIO™ (V
IO
) Control.................................................................................................................................................................24
Requirements for Asynchronous Read Operation (Non-Burst)..............................................................................................24
Requirements for Synchronous (Burst) Read Operation...........................................................................................................25
Continuous Burst .........................................................................................................................................................................25
8-, 16-, and 32-Word Linear Burst with Wrap Around ....................................................................................................27
8-, 16-, and 32-Word Linear Burst without Wrap Around .............................................................................................27
Programmable Wait State................................................................................................................................................................... 28
Configuration Register ......................................................................................................................................................................... 28
Handshaking Feature............................................................................................................................................................................. 28
Simultaneous Read/Write Operations with Zero Latency ....................................................................................................... 28
Writing Commands/Command Sequences.................................................................................................................................... 28
Accelerated Program and Erase Operations................................................................................................................................. 28
Write Buffer Programming Operation............................................................................................................................................ 29
Autoselect Mode.....................................................................................................................................................................................30
Advanced Sector Protection and Unprotection............................................................................................................................30
Sector Protection.....................................................................................................................................................................................31
Persistent Sector Protection ................................................................................................................................................................31
Persistent Protection Bit (PPB) ................................................................................................................................................32
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode ..........................................32
Dynamic Protection Bit (DYB) ................................................................................................................................................32
Persistent Sector Protection Mode Lock Bit..................................................................................................................................33
Password Sector Protection................................................................................................................................................................34
64-bit Password .......................................................................................................................................................................................34
Password Mode Lock Bit......................................................................................................................................................................34
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode......................................................35
Hardware Data Protection Mode......................................................................................................................................................35
Write Protect (WP#) .................................................................................................................................................................35
WP# Boot Sector Protection .............................................................................................................................................................35
Low VCC Write Inhibit ........................................................................................................................................................................36
2
S71NS128NA0/S71NS064NA0 Based MCPs
S71NS128_064NA0_00_A1 September 23, 2005
A d v a n c e
I n f o r m a t i o n
Write Pulse “Glitch” Protection ........................................................................................................................................................36
Logical Inhibit............................................................................................................................................................................................36
Power-Up Write Inhibit .............................................................................................................................................................36
Lock Register............................................................................................................................................................................................36
Standby Mode .........................................................................................................................................................................................37
Automatic Sleep Mode ..........................................................................................................................................................................37
RESET#: Hardware Reset Input .........................................................................................................................................................37
V
CC
Power-up and Power-down Sequencing .....................................................................................................................37
Output Disable Mode............................................................................................................................................................................37
SecSi™ (Secured Silicon) Sector Flash Memory Region...............................................................................................................37
Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory .................................................38
Customer SecSi Sector ...............................................................................................................................................................38
Common Flash Memory Interface (CFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Reading Array Data.................................................................................................................................................................................51
Set Configuration Register Command Sequence...........................................................................................................................51
Read Configuration Register Command Sequence .......................................................................................................................51
Read Mode Setting .......................................................................................................................................................................52
Programmable Wait State Configuration .............................................................................................................................52
Programmable Wait State .........................................................................................................................................................52
Handshaking ...................................................................................................................................................................................53
Burst Length Configuration .......................................................................................................................................................53
Burst Wrap Around ....................................................................................................................................................................53
RDY Configuration ......................................................................................................................................................................53
RDY Polarity ..................................................................................................................................................................................54
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Reset Command......................................................................................................................................................................................55
Autoselect Command Sequence .......................................................................................................................................................57
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence.....................................................................................................57
Unlock Bypass Command Sequence ..................................................................................................................................... 58
Program Command Sequence ........................................................................................................................................................... 58
Program Command Sequence ................................................................................................................................................. 58
Program Command Sequence (Unlock Bypass Mode) .................................................................................................... 58
Accelerated Program............................................................................................................................................................................ 58
Write Buffer Programming Command Sequence .........................................................................................................................59
Chip Erase Command Sequence .........................................................................................................................................................61
Chip Erase Command Sequence ..............................................................................................................................................61
Sector Erase Command Sequence.....................................................................................................................................................62
Sector Erase Command Sequence ..........................................................................................................................................62
Accelerated Sector Erase ..........................................................................................................................................................63
Erase Suspend/Erase Resume Commands...................................................................................................................................... 64
Program Suspend/Program Resume Commands ......................................................................................................................... 64
Lock Register Command Set Definitions ........................................................................................................................................65
Password Protection Command Set Definitions ..........................................................................................................................65
Non-Volatile Sector Protection Command Set Definitions ..................................................................................................... 66
Global Volatile Sector Protection Freeze Command Set.......................................................................................................... 68
Volatile Sector Protection Command Set...................................................................................................................................... 68
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DQ7: Data# Polling ................................................................................................................................................................................74
RDY: Ready .............................................................................................................................................................................................76
DQ6: Toggle Bit I....................................................................................................................................................................................76
DQ2: Toggle Bit II...................................................................................................................................................................................76
Reading Toggle Bits DQ6/DQ2 ......................................................................................................................................................... 78
DQ5: Exceeded Timing Limits ........................................................................................................................................................... 78
DQ3: Sector Erase Start Timeout State Indicator........................................................................................................................79
September 23, 2005 S71NS128_064NA0_00_A1
S71NS128NA0/S71NS064NA0 Based MCPs
3
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器件捷径:
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