S71WSxxxJ based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CellularRAM
PRELIMINARY
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Speed: 66MHz
Packages
— 8 x 11.6mm, 84 ball FBGA
Operating Temperature
— –25°C to +85°C
— –40°C to +85°C
General Description
The S71WS series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
One or more flash memory die
CellularRAM-compatible pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details:
Flash Memory Density
256Mb
64Mb
pSRAM
Density
32Mb
16Mb
S71WS256JC0
128Mb
S71WS128JC0
S71WS128JB0
S71WS128JA0
S71WS064JB0
S71WS064JA0
64Mb
Publication Number
S71WS256/128/064J_00
Revision
A
Amendment
0
Issue Date
November 10, 2004
P r e l i m i n a r y
Product Selector Guide
Device-Model#
S71WS064JA0-2A
S71WS064JB0-26
S71WS064JB0-2A
S71WS128JA0-AA
S71WS128JB0-AA
S71WS128JC0-AA
S71WS128JC0-A6
S71WS256JC0-TA
S71WS256JC0-T6
256Mb
128Mb
64Mb
Flash Speed pSRAM Speed
Flash Density pSRAM Density
(MHz)
(MHz/ns)
16Mb
32Mb
16Mb
32Mb
66
66/70
Supplier
CellularRAM Type 2
Cellular RAM Type 1
Cellular RAM Type 2
Cellular RAM Type 2
Cellular RAM Type 2
Cellular RAM Type 2
64Mb
Cellular RAM Type 1
Cellular RAM Type 2
Cellular RAM Type 1
FTA084
TLA084
TLC080
Package
2
S71WSxxxJ based MCPs
S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
S71WSxxxJ based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
Figure 1. Temporary Sector Unprotect Operation ................... 39
Figure 2. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 40
Table 7. SecSi™ Sector Addresses ...................................... 41
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Connection Diagram (CellularRAM Type-based) .7
Special Handling Instructions For FBGA Package ...................................8
Lookahead Connection Diagram . . . . . . . . . . . . . .9
Input/Output Descriptions . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 14
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ........................................................................................... 14
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................15
SecSi™ Sector Protection Bit ......................................................................42
Hardware Data Protection .........................................................................42
Write Protect (WP#) .......................................................................................42
Low V
CC
Write Inhibit ................................................................................. 43
Write Pulse “Glitch” Protection ............................................................... 43
Logical Inhibit ................................................................................................... 43
Power-Up Write Inhibit ............................................................................... 43
Common Flash Memory Interface (CFI) . . . . . . . 44
Table 8. CFI Query Identification String ................................ 44
Table 9. System Interface String ......................................... 45
Table 10. Device Geometry Definition................................... 45
Table 11. Primary Vendor-Specific Extended Query ................ 46
Table 12. WS128J Sector Address Table ............................... 47
Table 13. WS064J Sector Address Table ............................... 55
S29WS128/064J
General Description . . . . . . . . . . . . . . . . . . . . . . . . 18
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .20
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 22
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .24
Table 1. Device Bus Operations .......................................... 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 61
Reading Array Data ............................................................................................61
Set Configuration Register Command Sequence ......................................61
Figure 3. Synchronous/Asynchronous State Diagram.............. 62
Read Mode Setting ......................................................................................... 62
Programmable Wait State Configuration ...............................................62
Table 14. Programmable Wait State Settings ......................... 63
Standard wait-state Handshaking Option ............................................... 63
Table 15. Wait States for Standard wait-state Handshaking .... 63
Read Mode Configuration ........................................................................... 63
Table 16. Read Mode Settings ............................................. 64
VersatileIO™ (V
IO
) Control ............................................................................ 24
Requirements for Asynchronous Read Operation (Non-Burst) ......... 24
Requirements for Synchronous (Burst) Read Operation .......................25
8-, 16-, and 32-Word Linear Burst with Wrap Around ..................... 26
Table 2. Burst Address Groups ............................................ 26
Burst Active Clock Edge Configuration .................................................. 64
RDY Configuration ........................................................................................64
Table 17. Configuration Register .......................................... 65
Configuration Register ..................................................................................... 26
Handshaking ......................................................................................................... 26
Simultaneous Read/Write Operations with Zero Latency ....................27
Writing Commands/Command Sequences .................................................27
Accelerated Program Operation ...................................................................27
Autoselect Mode ................................................................................................ 28
Table 3. Autoselect Codes (High Voltage Method) ................. 29
Reset Command ................................................................................................. 65
Autoselect Command Sequence .................................................................... 65
Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence .............66
Program Command Sequence ........................................................................ 67
Unlock Bypass Command Sequence ........................................................ 67
Figure 4. Program Operation ............................................... 68
Chip Erase Command Sequence ...................................................................68
Sector Erase Command Sequence ................................................................69
Erase Suspend/Erase Resume Commands .................................................. 70
Figure 5. Erase Operation ................................................... 71
Sector/Sector Block Protection and Unprotection ................................. 29
Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses
for Protection/Unprotection ................................................. 29
Table 5. S29WS064J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 31
Sector Protection ...........................................................................................33
Persistent Sector Protection ...........................................................................33
Persistent Protection Bit (PPB) ..................................................................34
Persistent Protection Bit Lock (PPB Lock) .............................................34
Dynamic Protection Bit (DYB) ...................................................................34
Table 6. Sector Protection Schemes ..................................... 35
Persistent Sector Protection Mode Locking Bit ........................................36
Password Protection Mode .............................................................................36
Password and Password Mode Locking Bit ................................................36
64-bit Password ...................................................................................................37
Persistent Protection Bit Lock ........................................................................37
Standby Mode .......................................................................................................37
Automatic Sleep Mode ......................................................................................38
RESET#: Hardware Reset Input .................................................................38
Output Disable Mode ....................................................................................39
Password Program Command ........................................................................ 71
Password Verify Command .............................................................................. 71
Password Protection Mode Locking Bit Program Command .............. 72
Persistent Sector Protection Mode Locking Bit Program Command 72
SecSi™ Sector Protection Bit Program Command ................................... 72
PPB Lock Bit Set Command ............................................................................ 72
DPB Write/Erase/Status Command ............................................................. 73
Password Unlock Command .......................................................................... 73
PPB Program Command .................................................................................. 73
All PPB Erase Command .................................................................................. 74
PPB Status Command ....................................................................................... 74
PPB Lock Bit Status Command ...................................................................... 74
Command Definitions ....................................................................................... 75
Table 18. Command Definitions .......................................... 75
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 78
DQ7: Data# Polling ............................................................................................78
Figure 6. Data# Polling Algorithm ........................................ 79
DQ6: Toggle Bit I ...............................................................................................80
Figure 7. Toggle Bit Algorithm ............................................. 81
DQ2: Toggle Bit II ...............................................................................................81
November 10, 2004 S71WS256/128/064J_00_A0
3
P r e l i m i n a r y
Table 19. DQ6 and DQ2 Indications ..................................... 82
Reading Toggle Bits DQ6/DQ2 ..................................................................... 82
DQ5: Exceeded Timing Limits ........................................................................83
DQ3: Sector Erase Timer .................................................................................83
Table 20. Write Operation Status ......................................... 84
General Description . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 38. Functional Block Diagram .................................. 115
Table 22. Signal Descriptions ............................................ 116
Table 23. Bus Operations—Asynchronous Mode ................... 117
Table 24. Bus Operations—Burst Mode ............................... 118
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .85
Figure 8. Maximum Negative Overshoot Waveform ................. 85
Figure 9. Maximum Positive Overshoot Waveform .................. 85
Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Power-Up Initialization .....................................................................................118
Figure 39. Power-Up Initialization Timing............................ 119
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .87
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 10. Test Setup ......................................................... 88
Table 21. Test Specifications ............................................... 88
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . 119
Asynchronous Mode .........................................................................................119
Figure 40. READ Operation (ADV# LOW) ............................ 119
Figure 41. WRITE Operation (ADV# LOW)........................... 120
Page Mode READ Operation ........................................................................120
Figure 42. Page Mode READ Operation (ADV# LOW) ............ 121
Key to Switching Waveforms . . . . . . . . . . . . . . . 88
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 88
Figure 11. Input Waveforms and Measurement Levels............. 88
Burst Mode Operation .....................................................................................121
Figure 43. Burst Mode READ (4-word burst)........................ 122
Figure 44. Burst Mode WRITE (4-word burst) ...................... 122
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .89
V
CC
Power-up ..................................................................................................... 89
CLK Characterization ....................................................................................... 89
Figure 12. V
CC
Power-up Diagram ........................................ 89
Figure 13. CLK Characterization ........................................... 89
Mixed-Mode Operation ...................................................................................123
WAIT Operation ...............................................................................................123
Figure 45. Wired or WAIT Configuration.............................. 123
LB#/UB# Operation .........................................................................................124
Figure 46. Refresh Collision During READ Operation ............. 124
Figure 47. Refresh Collision During WRITE Operation............ 125
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .90
Synchronous/Burst Read @ V
IO
= 1.8 V ..................................................... 90
Figure 14. CLK Synchronous Burst Mode Read (rising active CLK).
91
Figure 15. CLK Synchronous Burst Mode Read (Falling Active Clock)
91
Figure 16. Synchronous Burst Mode Read.............................. 92
Figure 17. 8-word Linear Burst with Wrap Around................... 92
Figure 18. Linear Burst with RDY Set One Cycle Before Data .... 93
Figure 19. Asynchronous Mode Read with Latched Addresses... 95
Figure 20. Asynchronous Mode Read..................................... 95
Figure 21. Reset Timings..................................................... 96
Figure 22. Asynchronous Program Operation Timings: AVD#
Latched Addresses ............................................................. 98
Figure 23. Asynchronous Program Operation Timings: WE#
Latched Addresses ............................................................. 99
Figure 24. Synchronous Program Operation Timings: WE# Latched
Addresses ....................................................................... 100
Figure 25. Synchronous Program Operation Timings: CLK Latched
Addresses ....................................................................... 101
Figure 26. Chip/Sector Erase Command Sequence................ 102
Figure 27. Accelerated Unlock Bypass Programming Timing ... 103
Figure 28. Data# Polling Timings (During Embedded Algorithm)...
104
Figure 29. Toggle Bit Timings (During Embedded Algorithm).. 104
Figure 30. Synchronous Data Polling
Timings/Toggle Bit Timings................................................ 105
Figure 31. DQ2 vs. DQ6 .................................................... 105
Figure 32. Temporary Sector Unprotect Timing Diagram........ 106
Figure 33. Sector/Sector Block Protect and Unprotect Timing
Diagram.......................................................................... 107
Figure 34. Latency with Boundary Crossing.......................... 108
Figure 35. Latency with Boundary Crossing into Program/Erase
Bank .............................................................................. 109
Figure 36. Example of Wait States Insertion ........................ 110
Figure 37. Back-to-Back Read/Write Cycle Timings ............... 111
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 125
Standby Mode Operation ................................................................................125
Temperature Compensated Refresh ...........................................................125
Partial Array Refresh ........................................................................................126
Deep Power-Down Operation .....................................................................126
Configuration Registers . . . . . . . . . . . . . . . . . . . . 126
Access Using CRE .............................................................................................126
Figure 48. Configuration Register WRITE, Asynchronous Mode
Followed by READ............................................................ 127
Figure 49. Configuration Register WRITE, Synchronous Mode
Followed by READ0.......................................................... 128
Asynchronous Mode Read @ V
IO
= 1.8 V ................................................. 94
Erase/Program Operations @ V
IO
= 1.8 V ..................................................97
Bus Configuration Register .............................................................................128
Table 25. Bus Configuration Register Definition .................... 129
Table 26. Sequence and Burst Length ................................ 130
Burst Length (BCR[2:0]): Default = Continuous Burst .....................130
Burst Wrap (BCR[3]): Default = No Wrap ..........................................130
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength .............................................................................................................131
Table 27. Output Impedance ............................................. 131
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid .................................................................131
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ................131
Figure 50. WAIT Configuration (BCR[8] = 0) ....................... 131
Figure 51. WAIT Configuration (BCR[8] = 1) ....................... 132
Figure 52. WAIT Configuration During Burst Operation ......... 132
Latency Counter (BCR[13:11]): Default = Three-Clock Latency .....132
Table 28. Variable Latency Configuration Codes ................... 132
Figure 53. Latency Counter (Variable Initial Latency, No Refresh
Collision) ........................................................................ 133
Temporary Sector Unprotect .......................................................................106
Operating Mode (BCR[15]): Default = Asynchronous Operation . 133
Refresh Configuration Register ..................................................................... 133
Table 29. Refresh Configuration Register Mapping ................ 134
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh ....134
Table 30. 128Mb Address Patterns for PAR (RCR[4] = 1) ...... 134
Table 31. 64Mb Address Patterns for PAR (RCR[4] = 1) ........ 135
Table 32. 32Mb Address Patterns for PAR (RCR[4] = 1) ........ 135
CellularRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4
Deep Power-Down (RCR[4]): Default = DPD Disabled .................. 135
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation ........................................................................................................ 135
S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
Page Mode Operation (RCR[7]): Default = Disabled .........................135
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 136
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 137
Table 33. Electrical Characteristics and Operating Conditions .137
Table 34. Temperature Compensated Refresh Specifications and
Conditions .......................................................................138
Table 35. Partial Array Refresh Specifications and Conditions .138
Table 36. Deep Power-Down Specifications ..........................138
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 54. AC Input/Output Reference Waveform ................. 139
Figure 55. Output Load Circuit ........................................... 139
Table 37. Output Load Circuit ............................................139
Table 38. Asynchronous READ Cycle Timing Requirements .....140
Table 39. Burst READ Cycle Timing Requirements .................141
Table 40. Asynchronous WRITE Cycle Timing Requirements ...142
Table 41. Burst WRITE Cycle Timing Requirements ...............142
Timing Diagrams ................................................................................................ 143
Figure 56. Initialization Period............................................ 143
Table 42. Initialization Timing Parameters ...........................143
Figure 57. Asynchronous READ .......................................... 144
Table 43. Asynchronous READ Timing Parameters ................144
Figure 58. Asynchronous READ Using ADV# ........................ 146
Table 44. Asynchronous READ Timing
Parameters Using ADV# ....................................................146
Figure 59. Page Mode READ............................................... 148
Table 45. Asynchronous READ Timing Parameters—Page Mode
Operation ........................................................................148
Figure 60. Single-Access Burst READ
Operation—Variable Latency.............................................. 150
Table 46. Burst READ Timing Parameters—Single Access, Variable
Latency ...........................................................................150
Figure 61. Four-word Burst READ
Operation—Variable Latency.............................................. 152
Table 47. Burst READ Timing Parameters—4-word Burst .......153
Figure 62. Four-word Burst READ Operation (with LB#/UB#) . 154
Table 48. Burst READ Timing Parameters—4-word Burst with LB#/
UB# ...............................................................................155
Figure 63. READ Burst Suspend ......................................... 156
Table 49. Burst READ Timing Parameters—Burst Suspend .....156
Figure 64. Continuous Burst READ Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition ................................. 157
Table 50. Burst READ Timing Parameters—BCR[8] = 0 ..........157
Figure 65. CE#-Controlled Asynchronous WRITE .................. 158
Table 51. Asynchronous WRITE Timing Parameters—CE#-
Controlled .......................................................................158
Figure 66. LB#/UB#-Controlled Asynchronous WRITE ........... 160
Table 52. Asynchronous WRITE Timing Parameters—LB#/UB#-
Controlled .......................................................................160
Figure 67. WE#-Controlled Asynchronous WRITE.................. 162
Table 53. Asynchronous WRITE Timing Parameters—WE#-
Controlled .......................................................................162
Figure 68. Asynchronous WRITE Using ADV#....................... 164
Table 54. Asynchronous WRITE Timing
Parameters Using ADV# ....................................................165
Figure 69. Burst WRITE Operation ...................................... 166
Table 55. Burst WRITE Timing Parameters .......................... 167
Figure 70. Continuous Burst WRITE Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 168
Table 56. Burst WRITE Timing Parameters—BCR[8] = 0 ....... 168
Figure 71. Burst WRITE Followed by Burst READ.................. 169
Table 57. WRITE Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 169
Table 58. READ Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 169
Figure 72. Asynchronous WRITE Followed by Burst READ...... 170
Table 59. WRITE Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 171
Table 60. READ Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 171
Figure 73. Asynchronous WRITE (ADV# LOW) Followed By Burst
READ ............................................................................. 172
Table 61. Asynchronous WRITE Timing
Parameters—ADV# LOW .................................................. 172
Table 62. Burst READ Timing Parameters ............................ 173
Figure 74. Burst READ Followed by Asynchronous WRITE (WE#-
Controlled) ..................................................................... 174
Table 63. Burst READ Timing Parameters ............................ 175
Table 64. Asynchronous WRITE Timing Parameters—WE#
Controlled ....................................................................... 175
Figure 75. Burst READ Followed by Asynchronous WRITE Using
ADV#............................................................................. 176
Table 65. Burst READ Timing Parameters ............................ 177
Table 66. Asynchronous WRITE Timing Parameters
Using ADV# .................................................................... 177
Figure 76. Asynchronous WRITE Followed by Asynchronous READ—
ADV# LOW ..................................................................... 178
Table 67. WRITE Timing Parameters—ADV# LOW ................ 178
Table 68. READ Timing Parameters—ADV# LOW .................. 179
Figure 77. Asynchronous WRITE Followed by
Asynchronous READ......................................................... 180
Table 69. WRITE Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 180
Table 70. READ Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 181
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Introduction .........................................................................................................181
Asynchronous WRITE Operation ................................................................182
Figure 78. Extended Timing for t
CEM .............................................. 182
Figure 79. Extended Timing for t
TM ................................................ 182
Table 71. Extended Cycle Impact on READ and WRITE Cycles 182
Extended WRITE Timing— Asynchronous WRITE Operation .....182
Figure 80. Extended WRITE Operation................................ 183
Page Mode READ Operation ........................................................................183
Burst-Mode Operation ....................................................................................183
Summary ...............................................................................................................183
Revision Summary
November 10, 2004 S71WS256/128/064J_00_A0
5
FPGA/CPLD
