S71WS512Nx0/S71WS256Nx0 Based MCPs
Stacked Multi-chip Product (MCP)
256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write, Burst-mode
Flash Memory with 128/64Megabit (8M/4M x 16-Bit)
CELLULAR RAM
Datasheet
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Burst Speed: 54MHz
Packages: 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
-25°C to +85°C
-40°C to +85°C
ADVANCE
INFORMATION
General Description
The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
One or more flash memory die
Cellular RAM Type pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheet for
further details.
Flash Density
512Mb
pSRAM Density
128Mb
64Mb
32Mb
16Mb
S71WS512ND0
S71WS512NC0
256Mb
S71WS256ND0
S71WS256NC0
128Mb
64Mb
Publication Number
S71WS512/256Nx0_00
Revision
A
Amendment
0
Issue Date
November 9, 2004
A d v a n c e
I n f o r m a t i o n
S71WS512Nx0/S71WS256Nx0 Based MCPs
Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ................................................................................................... 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagrams
CellularRAM Based Pinout . . . . . . . . . . . . . . . . . . .7
MCP Look-Ahead Connection Diagram ........................................................8
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . .9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 11
256Mb WS256N Flash + 64Mb pSRAM ......................................................... 11
256Mb - WS256N Flash + 128 pSRAM ...........................................................11
2x 256Mb—WS512N Flash + 64Mb pSRAM ................................................12
2x256Mb—WS256N Flash + 128Mb pSRAM .............................................. 12
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 13
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ............................................................................................13
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ........................................................................................... 14
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm
MCP Compatible Package .................................................................................15
S29WSxxxN MirrorBit™ Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . 16
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 16
Application Notes ........................................................................................... 19
Specification Bulletins .................................................................................... 19
Drivers and Software Support .................................................................... 19
CAD Modeling Support ................................................................................ 19
Technical Support ........................................................................................... 19
Spansion LLC Locations ........................................................ 19
Table 4.2. S29WS128N Sector & Memory Address Map .......... 21
Table 4.3. S29WS064N Sector & Memory Address Map .......... 22
Table 5.4. Device Operations .............................................. 23
Table 5.7. Address Latency for 5 Wait States (≤ 68 MHz) ........ 25
Table 5.8. Address Latency for 4 Wait States (≤ 54 MHz) ........ 26
Table 5.9. Address Latency for 3 Wait States (≤ 40 MHz) ........ 26
Table 5.10. Address/Boundary Crossing Latency for 6 Wait States
(≤ 80 MHz) ....................................................................... 26
Table 5.11. Address/Boundary Crossing Latency for 5 Wait States
(≤ 68 MHz) ....................................................................... 26
Table 5.12. Address/Boundary Crossing Latency for 4 Wait States
(≤ 54 MHz) ....................................................................... 26
Table 5.13. Address/Boundary Crossing Latency for 3 Wait States
(≤ 40 MHz) ....................................................................... 26
Figure 5.2. Synchronous Read ............................................. 27
Table 5.14. Burst Address Groups ....................................... 28
Table 5.15. Configuration Register ....................................... 29
Table 5.16. Autoselect Addresses ........................................ 30
Table 5.17. Autoselect Entry ............................................... 30
Table 5.18. Autoselect Exit ................................................. 31
Figure 5.19. Single Word Program ........................................ 33
Table 5.20. Single Word Program ........................................ 34
Table 5.21. Write Buffer Program ........................................ 36
Figure 5.22. Write Buffer Programming Operation .................. 37
Table 5.23. Sector Erase .................................................... 39
Figure 5.24. Sector Erase Operation ..................................... 40
Table 5.25. Chip Erase ....................................................... 41
Table 5.26. Erase Suspend ................................................. 42
Table 5.27. Erase Resume .................................................. 42
Table 5.28. Program Suspend ............................................. 43
Table 5.29. Program Resume .............................................. 43
Table 5.30. Unlock Bypass Entry .......................................... 44
Table 5.31. Unlock Bypass Program ..................................... 45
Table 5.32. Unlock Bypass Reset ......................................... 45
Figure 5.33. Write Operation Status Flowchart....................... 47
Table 5.34. DQ6 and DQ2 Indications ................................... 49
Table 5.35. Write Operation Status ...................................... 50
Table 5.36. Reset .............................................................. 52
Figure 6.2. Lock Register Program Algorithm......................... 58
Table 8.2. SecSi Sector Entry .............................................. 63
Table 8.3. SecSi Sector Program .......................................... 64
Table 8.4. SecSi Sector Entry .............................................. 64
Figure 9.2. Maximum Positive Overshoot Waveform ............... 65
Figure 9.3. Test Setup........................................................ 66
Figure 9.4. Input Waveforms and Measurement Levels ........... 67
Figure 9.5. V
CC
Power-up Diagram....................................... 67
Figure 9.6. CLK Characterization.......................................... 69
Figure 9.7. CLK Synchronous Burst Mode Read...................... 71
Figure 9.8. 8-word Linear Burst with Wrap Around................. 72
Figure 9.9. 8-word Linear Burst without Wrap Around ............ 72
Figure 9.10. Linear Burst with RDY Set One Cycle Before Data 73
Figure 9.11. Asynchronous Mode Read ................................. 74
Figure 9.12. Reset Timings ................................................. 75
Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched
Addresses......................................................................... 77
Figure 9.13. Asynchronous Program Operation Timings: WE#
Latched Addresses............................................................. 78
Figure 9.14. Synchronous Program Operation Timings:
CLK Latched Addresses ...................................................... 79
Figure 9.15. Accelerated Unlock Bypass Programming Timing.. 80
Figure 9.16. Data# Polling Timings (During Embedded Algorithm)
80
Figure 9.17. Toggle Bit Timings (During Embedded Algorithm) 81
Figure 9.18. Synchronous Data Polling Timings/Toggle Bit Timings
81
Figure 9.19. DQ2 vs. DQ6................................................... 82
Figure 9.20. Latency with Boundary Crossing when
Frequency > 66 MHz.......................................................... 82
Figure 9.21. Latency with Boundary Crossing into Program/
Erase Bank ....................................................................... 83
Figure 9.22. Example of Wait States Insertion ....................... 84
Figure 9.23. Back-to-Back Read/Write Cycle Timings.............. 85
Table 10.2. Sector Protection Commands .............................. 90
Table 10.3. CFI Query Identification String ............................ 91
Table 10.4. System Interface String ..................................... 92
Table 10.5. Device Geometry Definition ................................ 92
Table 10.6. Primary Vendor-Specific Extended Query ............. 93
CellularRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
General Description . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 1. Functional Block Diagram ...................................... 99
Table 1. Signal Descriptions .............................................. 100
Table 2. Bus Operations—Asynchronous Mode ..................... 101
Table 3. Bus Operations—Burst Mode ................................. 102
Functional Description . . . . . . . . . . . . . . . . . . . . 102
Power-Up Initialization ....................................................................................103
Figure 2. Power-Up Initialization Timing.............................. 103
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . 103
Asynchronous Mode ........................................................................................103
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S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 November 9, 2004
A d v a n c e
I n f o r m a t i o n
Figure 3. READ Operation (ADV# LOW)............................... 104
Figure 4. WRITE Operation (ADV# LOW) ............................. 104
Page Mode READ Operation ........................................................................ 105
Figure 5. Page Mode READ Operation (ADV# LOW)............... 105
Burst Mode Operation .................................................................................... 105
Figure 6. Burst Mode READ (4-word burst) .......................... 106
Figure 7. Burst Mode WRITE (4-word burst)......................... 107
Table 16. Output Load Circuit ............................................ 124
Table 17. Asynchronous READ Cycle Timing Requirements .... 125
Table 18. Burst READ Cycle Timing Requirements ................ 126
Table 19. Asynchronous WRITE Cycle Timing Requirements .. 127
Table 20. Burst WRITE Cycle Timing Requirements .............. 128
Timing Diagrams ................................................................................................128
Figure 19. Initialization Period ........................................... 128
Table 21. Initialization Timing Parameters ........................... 128
Figure 20. Asynchronous READ.......................................... 129
Table 22. Asynchronous READ Timing Parameters ................ 130
Figure 21. Asynchronous READ Using ADV#........................ 131
Table 23. Asynchronous READ Timing Parameters Using ADV# ....
132
Figure 22. Page Mode READ.............................................. 133
Table 24. Asynchronous READ Timing Parameters—Page Mode
Operation ....................................................................... 134
Figure 23. Single-Access Burst READ Operation—Variable Latency
135
Table 25. Burst READ Timing Parameters—Single Access, Variable
Latency .......................................................................... 136
Figure 24. Four-word Burst READ Operation—Variable Latency .....
137
Table 26. Burst READ Timing Parameters—4-word Burst ....... 138
Figure 25. Four-word Burst READ Operation (with LB#/UB#) 139
Table 27. Burst READ Timing Parameters—4-word Burst with LB#/
UB# ............................................................................... 140
Figure 26. READ Burst Suspend......................................... 141
Table 28. Burst READ Timing Parameters—Burst Suspend ..... 142
Figure 27. Continuous Burst READ Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 143
Table 29. Burst READ Timing Parameters—BCR[8] = 0 ......... 143
Figure 28. CE#-Controlled Asynchronous WRITE.................. 144
Table 30. Asynchronous WRITE Timing Parameters—CE#-
Controlled ....................................................................... 145
Figure 29. LB#/UB#-Controlled Asynchronous WRITE .......... 146
Table 31. Asynchronous WRITE Timing Parameters—LB#/UB#-
Controlled ....................................................................... 147
Figure 30. WE#-Controlled Asynchronous WRITE................. 148
Table 32. Asynchronous WRITE Timing Parameters—WE#-
Controlled ....................................................................... 149
Figure 31. Asynchronous WRITE Using ADV# ...................... 150
Table 33. Asynchronous WRITE Timing Parameters Using ADV# ..
151
Figure 32. Burst WRITE Operation ..................................... 152
Table 34. Burst WRITE Timing Parameters .......................... 153
Figure 33. Continuous Burst WRITE Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 154
Table 35. Burst WRITE Timing Parameters—BCR[8] = 0 ....... 154
Figure 34. Burst WRITE Followed by Burst READ.................. 155
Table 36. WRITE Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 155
Table 37. READ Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 156
Figure 35. Asynchronous WRITE Followed by Burst READ...... 157
Table 38. WRITE Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 158
Table 39. READ Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 158
Figure 36. Asynchronous WRITE (ADV# LOW) Followed By Burst
READ ............................................................................. 159
Table 40. Asynchronous WRITE Timing Parameters—ADV# LOW ..
160
Table 41. Burst READ Timing Parameters ............................ 160
Figure 37. Burst READ Followed by Asynchronous WRITE (WE#-
Controlled) ..................................................................... 161
Table 42. Burst READ Timing Parameters ............................ 162
Mixed-Mode Operation .................................................................................. 107
WAIT Operation ..............................................................................................108
Figure 8. Wired or WAIT Configuration ................................ 108
LB#/UB# Operation .........................................................................................108
Figure 9. Refresh Collision During READ Operation................ 109
Figure 10. Refresh Collision During WRITE Operation ............ 110
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 110
Standby Mode Operation ................................................................................110
Temperature Compensated Refresh ...........................................................110
Partial Array Refresh ......................................................................................... 111
Deep Power-Down Operation ....................................................................... 111
Configuration Registers . . . . . . . . . . . . . . . . . . . . 111
Access Using CRE ............................................................................................... 111
Figure 11. Configuration Register WRITE, Asynchronous Mode
Followed by READ ............................................................ 112
Figure 12. Configuration Register WRITE, Synchronous Mode
Followed by READ0........................................................... 113
Bus Configuration Register ............................................................................. 114
Table 4. Bus Configuration Register Definition ......................114
Table 5. Sequence and Burst Length ...................................115
Burst Length (BCR[2:0]): Default = Continuous Burst ...................... 115
Burst Wrap (BCR[3]): Default = No Wrap .......................................... 115
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength ............................................................................................................. 116
Table 6. Output Impedance ...............................................116
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid ................................................................ 116
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ................ 116
Figure 13. WAIT Configuration (BCR[8] = 0)........................ 116
Figure 14. WAIT Configuration (BCR[8] = 1)........................ 117
Figure 15. WAIT Configuration During Burst Operation .......... 117
Latency Counter (BCR[13:11]): Default = Three-Clock Latency ...... 117
Table 7. Variable Latency Configuration Codes .....................117
Figure 16. Latency Counter (Variable Initial Latency, No Refresh
Collision)......................................................................... 118
Operating Mode (BCR[15]): Default = Asynchronous Operation ..118
Refresh Configuration Register .....................................................................118
Table 8. Refresh Configuration Register Mapping ..................119
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh ..... 119
Table 9. 128Mb Address Patterns for PAR (RCR[4] = 1) .........119
Table 10. 64Mb Address Patterns for PAR (RCR[4] = 1) .........120
Table 11. 32Mb Address Patterns for PAR (RCR[4] = 1) .........120
Deep Power-Down (RCR[4]): Default = DPD Disabled .................120
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation ........................................................................................................120
Page Mode Operation (RCR[7]): Default = Disabled ........................120
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 121
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 122
Table 12. Electrical Characteristics and Operating Conditions .122
Table 13. Temperature Compensated Refresh Specifications and
Conditions .......................................................................123
Table 14. Partial Array Refresh Specifications and Conditions .123
Table 15. Deep Power-Down Specifications ..........................123
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 17. AC Input/Output Reference Waveform ................. 124
Figure 18. Output Load Circuit ........................................... 124
November 9, 2004 S71WS512/256Nx0_00A0
S71WS512Nx0/S71WS256Nx0
3
A d v a n c e
I n f o r m a t i o n
Table 43. Asynchronous WRITE Timing Parameters—WE#
Controlled .......................................................................162
Figure 38. Burst READ Followed by Asynchronous WRITE Using
ADV# ............................................................................. 163
Table 44. Burst READ Timing Parameters ............................164
Table 45. Asynchronous WRITE Timing Parameters Using ADV# ..
165
Figure 39. Asynchronous WRITE Followed by Asynchronous READ—
ADV# LOW...................................................................... 166
Table 46. WRITE Timing Parameters—ADV# LOW .................167
Table 47. READ Timing Parameters—ADV# LOW ..................167
Figure 40. Asynchronous WRITE Followed by Asynchronous READ
168
Table 48. WRITE Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ........................................169
Table 49. READ Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 169
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Introduction ........................................................................................................170
Asynchronous WRITE Operation ................................................................170
Figure 41. Extended Timing for t
CEM .............................................. 170
Figure 42. Extended Timing for t
TM ................................................ 170
Table 50. Extended Cycle Impact on READ and WRITE Cycles 170
Extended WRITE Timing— Asynchronous WRITE Operation ......171
Figure 43. Extended WRITE Operation................................ 171
Page Mode READ Operation .........................................................................171
Burst-Mode Operation .....................................................................................171
Summary ...............................................................................................................172
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 173
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S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 November 9, 2004
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
WS256N + 64 pSRAM
Device-Model
S71WS256NC0-AK
S71WS256NC0-AP
S71WS256NC0-AB
S71WS256NC0-AF
64M
54
54
pSRAM
density
Flash Speed
pSRAM
MHz
speed MHz
DYB Bits - Power Up
0 (Protected)
1(Unprotected [Default State])
0 (Protected)
1(Unprotected [Default State])
Supplier
CellularRAM 2
TLA084
CellularRAM 1
Package
WS256N + 128 pSRAM
Device-Model
S71WS256ND0-EK
128M
S71WS256ND0-EP
54
54
1 (Unprotected [Default state])
pSRAM
density
Flash Speed
pSRAM
MHz
speed MHz
DYB Bits - Power Up
0 (Protected)
Supplier
CellularRAM 2
Package
TSD084
9x12x1.2
WS512N + 64 pSRAM
pSRAM
density
Flash Speed
MHz
pSRAM
speed
MHz
Device-Model
S71WS512NC0-AK
S71WS512NC0-AP
S71WS512NC0-AB
S71WS512NC0-AF
DYB Bits - Power Up
0 (Protected)
Supplier
CellularRAM 2
Package
64Mb
54
54
1(Unprotected [Default State])
0 (Protected)
1(Unprotected [Default State])
TLA084
CellularRAM 1
WS512N + 128 pSRAM
Device-Model
S71WS512ND0-YK
S71WS512ND0-YP
pSRAM
density
128Mb
Flash Speed
pSRAM
MHz
speed MHz
54
54
DYB Bits - Power Up
0
1
Supplier
CellularRAM 2
Package
FEA084
9x12x1.4
November 9, 2004 S71WS512/256Nx0_00_A0
S71WS512Nx0/S71WS256Nx0
5
模拟与混合信号
