SA572
Programmable Analog
Compandor
The SA572 is a dual-channel, high-performance gain control
circuit in which either channel may be used for dynamic range
compression or expansion. Each channel has a full-wave rectifier to
detect the average value of input signal, a linearized, temperature-
compensated variable gain cell (DG) and a dynamic time constant
buffer. The buffer permits independent control of dynamic attack and
recovery time with minimum external components and improved low
frequency gain control ripple distortion over previous compandors.
The SA572 is intended for noise reduction in high-performance
audio systems. It can also be used in a wide range of communication
systems and video recording applications.
Features
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MARKING DIAGRAMS
16
16
1
SOIC−16 WB
D SUFFIX
CASE 751G
SA572D
AWLYYWWG
•
Independent Control of Attack and Recovery Time
•
Improved Low Frequency Gain Control Ripple
•
Complementary Gain Compression and Expansion with
•
•
•
•
•
•
•
•
•
•
•
•
•
•
External Op Amp
Wide Dynamic Range
−
Greater than 110 dB
Temperature-Compensated Gain Control
Low Distortion Gain Cell
Low Noise
−
6.0
mV
Typical
Wide Supply Voltage Range
−
6.0 V-22 V
System Level Adjustable with External Components
Pb−Free Packages are Available*
16
1
16
SA572N
AWLYYWWG
1
16
SA
572
ALYW
G
G
1
1
PDIP−16
N SUFFIX
CASE 648
16
1
TSSOP−16
DTB SUFFIX
CASE 948F
Applications
Dynamic Noise Reduction System
Voltage Control Amplifier
Stereo Expandor
Automatic Level Control
High-Level Limiter
Low-Level Noise Gate
State Variable Filter
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
D, N, DTB Packages*
TRACK TRIM A 1
RECOV. CAP A 2
RECT. IN A 3
ATTACK CAP A 4
DG
OUT A 5
THD TRIM A 6
DG
IN A 7
GND 8
16
V
CC
15 TRACK TRIM B
14 RECOV. CAP B
13 RECT. IN B
12 ATTACK CAP B
11
DG
OUT B
10 THD TRIM B
9
DG
IN B
*D package released in large SO (SOL) package only.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
March, 2006
−
Rev. 2
1
Publication Order Number:
SA572/D
SA572
R
1
(7,9)
(6,10)
500
Ω
GAIN CELL
6.8kW
DG
(5,11)
(1,15)
(3,13)
270
Ω
−
+
RECTIFIER
10kW
−
+
BUFFER
10kW
(16)
P.S.
(8)
(4,12)
(2,14)
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
TRACK TRIM A
RECOV. CAP A
RECT. IN A
ATTACK CAP A
DG
OUT A
THD TRIM A
DG
IN A
GND
DG
IN B
THD TRIM B
DG
OUT B
ATTACK CAP B
RECT. IN B
RECOV. CAP B
TRACK TRIM B
V
CC
Tracking Trim A
Recovery Capacitor A
Rectifier A Input
Attack Capacitor A
Variable Gain Cell A Output
Total Harmonic Distortion Trim A
Variable Gain Cell A Input
Ground
Variable Gain Cell B Input
Total Harmonic Distortion Trim B
Variable Gain Cell B Output
Attack Capacitor B
Rectifier B Input
Recovery Capacitor B
Tracking Trim B
Positive Power Supply
Description
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2
SA572
MAXIMUM RATINGS
Rating
Supply Voltage
Operating Temperature Range
Operating Junction Temperature
Power Dissipation
Thermal Resistance, Junction−to−Ambient
N Package
D Package
DTB Package
Symbol
V
CC
T
A
T
J
P
D
R
qJA
Value
22
−40
to +85
150
500
75
105
133
Unit
V
DC
°C
°C
mW
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
signals at unity gain level (0 dB) = 100 mV
RMS
at 1.0 kHz; V
1
= V
2
; R
2
= 3.3 kW; R
3
= 17.3 kW, unless otherwise noted.
Characteristic
Supply Voltage
Supply Current
Internal Voltage Reference
Total Harmonic Distortion (Untrimmed)
Total Harmonic Distortion (Trimmed)
Total Harmonic Distortion (Trimmed)
No Signal Output Noise
DC Level Shift (Untrimmed)
Unity Gain Level
Large-Signal Distortion
Tracking Error
(Measured relative to value at unity gain) =
[V
O
−V
O
(unity gain)] dB−V
2
dB
Channel Crosstalk
Symbol
V
CC
I
CC
V
R
THD
THD
THD
Test Conditions
−
No Signal
−
1.0 kHz, C
A
= 1.0
mF
1.0 kHz, C
R
= 10
mF
100 Hz
Input to V
1
and V
2
grounded (20−20 kHz)
Input change from no
signal to 100 mV
RMS
−
V
1
= V
2
= 400 mV
Rectifier Input
V
2
= +6.0 dB, V
1
= 0 dB
V
2
=
−30
dB, V
1
= 0 dB
200 mV
RMS
into
channel A, measured
output on channel B
PSRR
120 Hz
Min
6.0
−
2.3
−
−
−
−
−
−1.5
−
−
−
60
Typ
−
−
2.5
0.2
0.05
0.25
6.0
"20
0
0.7
"0.2
"0.5
−
DC ELECTRICAL CHARACTERISTICS
Standard test conditions, V
CC
= 15 V, T
A
= 25°C; Expandor mode (see Test Circuit). Input
Max
22
6.3
2.7
1.0
−
−
25
"50
+1.5
3.0
Unit
V
DC
mA
V
DC
%
%
%
mV
mV
dB
%
dB
dB
dB
−2.5,
+1.6
−
Power Supply Rejection Ratio
−
1mF
1%
R
3
70
−
100W
+
22mF
dB
−15V
2.2mF
V
1
(7,9)
6.8kW
DG
(5,11)
82kW
17.3kW
5W
C
R
= 10mF
−
(2,14)
(6,10)
BUFFER
1kW
+
2.2k
+
2.2mF
270pF
NE5234
V
0
(4,12)
C
A
= 1mF
(8)
(1,15)
2.2mF
V
2
3.3kW (3,13)
R
2
1%
RECTIFIER
(16)
0.1mF
+15V
+
22mF
Figure 2. Test Circuit
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3
SA572
Audio Signal Processing IC Combines VCA and
Fast Attack/Slow Recovery Level Sensor
In high-performance audio gain control applications, it
is desirable to independently control the attack and
recovery time of the gain control signal. This is true, for
example, in compandor applications for noise reduction. In
high end systems the input signal is usually split into two
or more frequency bands to optimize the dynamic behavior
for each band. This reduces low frequency distortion due
to control signal ripple, phase distortion, high frequency
channel overload and noise modulation. Because of the
expense in hardware, multiple band signal processing up to
now was limited to professional audio applications.
With the introduction of the SA572 this high-
performance noise reduction concept becomes feasible for
consumer hi fi applications. The SA572 is a dual channel
gain control IC. Each channel has a linearized,
temperature-compensated gain cell and an improved level
sensor. In conjunction with an external low noise op amp
for current-to-voltage conversion, the VCA features low
distortion, low noise and wide dynamic range.
The novel level sensor which provides gain control
current for the VCA gives lower gain control ripple and
independent control of fast attack, slow recovery dynamic
response. An attack capacitor C
A
with an internal 10 kW
resistor R
A
defines the attack time
t
A
. The recovery time
t
R
of a tone burst is defined by a recovery capacitor C
R
and
an internal 10 kW resistor R
R
. Typical attack time of 4.0 ms
for the high-frequency spectrum and 40 ms for the low
frequency band can be obtained with 0.1
mF
and 1.0
mF
attack capacitors, respectively. Recovery time of 200 ms
can be obtained with a 4.7
mF
recovery capacitor for a
100 Hz signal, the third harmonic distortion is improved by
more than 10 dB over the simple RC ripple filter with a
single 1.0
mF
attack and recovery capacitor, while the
attack time remains the same.
The SA572 is assembled in a standard 16-pin dual in-line
plastic package and in oversized SOL package. It operates
over a wide supply range from 6.0 V to 22 V. Supply
current is less than 6.0 mA. The SA572 is designed for
applications from
−40°C
to +85°C.
BASIC APPLICATIONS
Description
The SA572 consists of two linearized, temperature-
compensated gain cells (DG), each with a full-wave
rectifier and a buffer amplifier as shown in the block
diagram. The two channels share a 2.5 V common bias
reference derived from the power supply but otherwise
operate independently. Because of inherent low distortion,
low noise and the capability to linearize large signals, a
wide dynamic range can be obtained. The buffer amplifiers
are provided to permit control of attack time and recovery
time independent of each other. Partitioned as shown in the
block diagram, the IC allows flexibility in the design of
system levels that optimize DC shift, ripple distortion,
tracking accuracy and noise floor for a wide range of
application requirements.
Gain Cell
V
T
I
n
1
I
2 G
)
1
I
O
2
*
V
T
I
n
I
S
1I
*
1I
2
G
2
O
I
S
(eq. 1)
+
V
T
I
n
I
2
*
I
1
*
I
IN
I
1
)
I
IN
*
V
T
I
n
I
S
I
S
where I
IN
+
V
IN
R
1
R
1
= 6.8 kW
I
1
= 140
mA
I
2
= 280
mA
I
O
is the differential output current of the gain cell and I
G
is the gain control current of the gain cell.
If all transistors Q
1
through Q
4
are of the same size,
equation 1 can be simplified to:
I
O
+
2
@
I
IN
@
I
G
*
1 I
2
*
2I
1
@
I
G
I
2
I
2
(eq. 2)
Figure 3 shows the circuit configuration of the gain cell.
Bases of the differential pairs Q
1
-Q
2
and Q
3
-Q
4
are both
tied to the output and inputs of OPA A
1
. The negative
feedback through Q
1
holds the V
BE
of Q
1
-Q
2
and the V
BE
of Q
3
-Q
4
equal. The following relationship can be derived
from the transistor model equation in the forward active
region.
DV
BE
Q3Q4
+
D
BE
Q1Q2
(V
BE
= V
T
I
IN
IC/IS)
The first term of equation 2 shows the multiplier
relationship of a linearized two quadrant transconductance
amplifier. The second term is the gain control feedthrough
due to the mismatch of devices. In the design, this has been
minimized by large matched devices and careful layout.
Offset voltage is caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be
trimmed out by feeding a current source within
"25
mA
into the THD trim pin.
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4
SA572
The residual distortion is third harmonic distortion and
is caused by gain control ripple. In a compandor system,
available control of fast attack and slow recovery improve
ripple distortion significantly. At the unity gain level of
100 mV, the gain cell gives THD (total harmonic
distortion) of 0.17% typ. Output noise with no input signals
is only 6.0
mV
in the audio spectrum (10 Hz-20 kHz). The
output current I
O
must feed the virtual ground input of an
operational amplifier with a resistor from output to
inverting input. The non-inverting input of the operational
amplifier has to be biased at V
REF
if the output current I
O
is DC coupled.
V+
1
1
I
)
I
2
G
2
O
I
1
140mA
I
O
A1
+
Q
4
Q
3
−
Q
1
Q
2
R
1
6.8kW
I
G
THD
TRIM
V
REF
V
IN
I
2
280mA
Figure 3. Basic Gain Cell Schematic
Rectifier
V+
I
+
V IN
*
V REF
R2
The rectifier is a full-wave design as shown in Figure 4.
The input voltage is converted to current through the input
resistor R
2
and turns on either Q
5
or Q
6
depending on the
signal polarity. Deadband of the voltage to current
converter is reduced by the loop gain of the gain block A
2
.
If AC coupling is used, the rectifier error comes only from
input bias current of gain block A
2
. The input bias current
is typically about 70 nA. Frequency response of the gain
block A
2
also causes second-order error at high frequency.
The collector current of Q
6
is mirrored and summed at the
collector of Q
5
to form the full wave rectified output
current I
R
. The rectifier transfer function is:
I
R
+
V
IN
*
V
REF
R
2
(eq. 3)
R
V
REF
+
A2
−
Q
5
D
7
Q
6
R
2
V
IN
If V
IN
is AC-coupled, then the equation will be reduced
to:
I
RAC
+
V
IN
(AVG)
R
2
The internal bias scheme limits the maximum output
current I
R
to be around 300
mA.
Within a
"1.0
dB error
band the input range of the rectifier is about 52 dB.
Figure 4. Simplified Rectifier Schematic
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5
