INTEGRATED CIRCUITS
DATA SHEET
SAA7205H
MPEG-2 systems demultiplexer
Preliminary specification
File under Integrated Circuits, IC02
1997 Jan 21
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.11.1
7.1.11.2
7.1.11.3
7.2
7.3
7.4
7.5
7.6
7.7
7.8
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Functional overview
MPEG-2 syntax parser
Error handling
Teletext filter
Generic data filter
High speed data filter
Video data filter
Audio data filter
Program clock reference processor
Time stamp processors
FIFO buffers
Microcontroller interface
Short filters
Long filters
Subtitling filter
MPEG-2 systems parsing
Error handling
Interfacing to the external descrambler
High speed data interfacing
Interfacing to Philips SAA7201 video decoder
Interfacing to a third party video decoder
Interfacing to SAA2500 and third party audio
decoders
7.11
7.12
7.13
7.14
7.14.1
7.14.2
7.14.3
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
7.9
7.10
SAA7205H
Interfacing to combined audio/video decoders
Interfacing to SAA9042 and SAA5270 teletext
decoders and SAA7183 EURO-DENC
Program clock reference processing
Time stamp processing (PTS/DTS)
Output buffering for audio and video
Microcontroller interfacing
Short filter module
Long filter module
Subtitling filter
PROGRAMMING THE DEMULTIPLEXER
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
APPENDIX
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1997 Jan 21
2
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
1
FEATURES
SAA7205H
Audio; third party audio decoder, or Philips SAA2500
compatible
Audio/video; third party combined A/V decoder
compatible, (programmable)
Teletext; a Teletext Clock/Teletext Data (TTC/TTD)
based serial interface to selected teletext decoders
(e.g. SAA9042). Alternatively, this interface can be
programmed to provide data for Vertical Blanking
Interval (VBI) insertion of teletext data. The interface
therefore includes a teletext data request input (TTR).
In this mode, the interface is compatible with the
SAA7183 (EURO-DENC) TXT interface.
HS Data; high-speed data output, outputting entire
transport packets, packet payloads, PES packet
payloads, or sections (programmable) at byte clock
frequency (9 MHz). In the test mode it is capable of
outputting copies of either video, audio or other data
streams (programmable).
HS pins are combined with the general purpose
interface. The general purpose interface is bidirectional,
and can therefore, be used as an alternative transport
stream input.
•
Descrambler; 8-bit wide data input interface, combined
with the modem input bus. A descrambler device may
output a descrambled transport stream at 9 MByte/s.
A 9 MHz descrambler clock is generated and output by
the demultiplexer.
•
Microcontroller support; only for control, no specific
demultiplexing tasks are performed by the
microcontroller. However, parsing and processing of
Program Specific Information (PSI), and Service
Information (SI) is left to the microcontroller.
•
Error handling; stream dependent error handling
algorithms, invoked either if the PKTBAD/PKTBAD input
signal is set, or if the transport_error_indicator bit
(MPEG-2 syntax) is set or if the parser detects an
MPEG-2 syntax error. Different handling algorithms are
applied for the various output ports.
•
Input data fully compliant with the Transport Stream
(TS) definition of the MPEG-2 systems specification
(International Standard; November 1994)
•
Input data signals: Forward Error Correction (FEC) or
descrambler interface
– modem data input bus (8-bit wide)
PKTDAT7 to PKTDAT0
– valid input data indicator (PKTDATV)
– erroneous packet indicator (PKTBAD/PKTBAD)
– first packet byte indicator (PKTSYNC)
– byte strobe signal [for the asynchronous mode only
(PKTBCLK)]
•
The interface can be configured to either of two modes:
– asynchronous mode; PKTBCLK < 9 MHz, for
connection to a modem (e.g. FEC)
– synchronous mode; PKTBCLK is not used for
connection to an external descrambler operating at
9 MHz. The descrambler chip clock (9 MHz; 33%
duty cycle) is generated and output to the
demultiplexer.
The descrambler chip clock [DCLK (9 MHz, 33% duty
cycle)] is generated and output by the demultiplexer
•
External memory; standard 32K
×
8-bit static RAM.
Required typical access time
≤
50 ns, write pulse width
(t
WP
)
≤
35 ns.
•
Effective bit rate: f
bit
≤
72 MHz
•
Control Interface; 8-bit multiplexed data/address
(MDAT7 to MDAT0), memory mapped I/O (P90CE201
microcontroller parallel bus compatible), in combination
with two microcontroller interrupt signals (IRQ and NMI).
In addition, a number of address input pins
(MA9 to MA2) allow direct access to a selected set of
demultiplexer registers.
•
Output ports:
Video; two alternative applications;
– third party video decoder compatible (master or slave
horizontal or vertical sync generation)
– Philips SAA7201 compatible (via general purpose
output)
1997 Jan 21
3
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
2
GENERAL DESCRIPTION
SAA7205H
This document specifies the MPEG-2 systems demultiplexer IC, SAA7205H, for use in MPEG-2 based digital TV
receivers, possibly incorporating conditional access. Such receivers are to be implemented in, for instance, a Digital
Video Broadcasting (DVB) set-top box, or Integrated Receiver Decoder (IRD). An example of a
demultiplexer/descrambler system configuration, containing a channel decoder module, source decoders, a system
microcontroller and a conditional access system is shown in Fig.1. The main function of the demultiplexer is to separate
relevant data from an incoming MPEG-2 systems compliant data stream and pass it to both the individual source
decoders and to the system microcontroller. To support descrambling, the demultiplexer interfaces with the descrambler
part of a conditional access system (optional). The demultiplexer therefore generates a 9 MHz descrambler chip clock.
3
QUICK REFERENCE DATA
SYMBOL
V
DDD
V
DDD(core)
P
tot
f
CLK
T
amb
4
PARAMETER
digital supply voltage
digital supply voltage for core
total power consumption
clock frequency
operating ambient temperature
f
byte
≤
9 MHz
CONDITIONS
MIN.
4.5
3.0
−
−
0
TYP.
5.0
3.3
−
−
−
MAX.
5.5
3.6
380
27
70
V
V
mW
MHz
°C
UNIT
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
QFP128
DESCRIPTION
plastic quad flat package; 128 leads (lead length 1.6 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT320-2
SAA7205H
handbook, full pagewidth
CONDITIONAL
ACCESS
SYSTEM
MICROCONTROLLER
AUDIO
SOURCE
DECODER
DEMODULATOR PLUS
FORWARD ERROR
CORRECTOR
(AND DESCRAMBLER)
SAA7205H
VIDEO
SOURCE
DECODER
9 MHz DCLK
32K x 8
SRAM
TELETEXT
DECODER
MGG374
Fig.1 Demultiplexer system configuration.
1997 Jan 21
4
5
handbook, full pagewidth
1997 Jan 21
MDAT0
to
CSVID
MA10
MA1
IRQ
MDAT7
MA2
VO7
to
to
R/W
MA0
NMI
CSDEM
MA9
VO0
98
97
87
54
68
75
71, 65,
72 66
86
101 102
74
73
70
RAMIO3
RAMA6,
to
OERAM RAMIO7 RAMA14 RAMA12 RAMA10 RAMA7
RAMIO2
RAMA0
RAMA9,
to
to
WERAM RAMIO0 RAMA13 RAMA11 RAMA8 RAMA5
Philips Semiconductors
BLOCK DIAGRAM
VSSD(core)
MICROCONTROLLER INTERFACE
RAM INTERFACE
16, 85
1
to
8
77 100 99
to
84
88
to
95
49
to
53
55 69
to
57
59
to
64
VDDD(core)
23, 76
VDDD1 to VDDD6
SHORT FILTER
MODULE
LONG FILTER
MODULE
SUBTITLING/
PRIVATE FILTER
9, 34, 41,
58, 96, 120
VSSD1 to VSSD7
32, 36, 48, 67,
105, 113, 126
TTR
37
GPO7 to GPO0
24 to 31
DCLK
119
PKTBCLK
118
PKTDAT7 to PKTDAT4
ERROR
HANDLING
TXT
FILTER
H/S DATA
FILTER
109 to 112
MPEG-2 systems demultiplexer
PKTDAT3 to PKTDAT0
VIDEO
DATA
FILTER
114 to 117
GENERIC
DATA
FILTER
PKTDATV
107
PKTBAD/PKTBAD
108
TRANSPORT
STREAM
AND
AF PARSER
AUDIO
DATA
FILTER
PKTSYNC
106
5
PRESENTATION/
DECODING
TIME STAMP
PROCESSOR
PROGRAM CLOCK
REFERENCE
PROCESSOR
PRESENTATION/
DECODING
TIME STAMP
PROCESSOR
TTD
38
TTC
39
HSE
20
HSV
21
HSSYNC
22
GPV
17
GPST
18
GPSYNC
19
CCLKI
35
TC0/TDI
BUFFER
CONTROL
121
SAA7205H
BUFFER
CONTROL
TDO
122
TMS
123
TC1/TCLK
124
TRST
40
VIN
EVEN/ODD
47
42
43
125
TEST CONTROL BLOCK
FOR
BOUNDARY SCAN TEST
AND
SCAN TEST
POR
103
45
46
CLK13.5
VSYNC
CbREF
128 127 104 44
CLKP
VREQ
COMSYNC
VSEL
AUDECLK
33
PWMO
10
11
AUE
15
14
AUDATV
AUDATR
AUDATCLK
13
12
MGG373
HSYNC
AUDAT
Preliminary specification
SAA7205H
Fig.2 Block diagram.
