NXP Semiconductors
Data Sheet: Technical Data
Document Number SAC57D54H
Rev. 7, 05/2017
SAC57D54H
Features
• ARM™ Cortex-A5, 32-bit CPU
– Supports ARMv7- ISA
– 32 KB Instruction cache, 32 KB Data cache
– NEON SIMD Media Processing Engine
– FPU supporting double precision floating point
operations
– Memory Management Unit
– GIC Interrupt Controller
– Up to 320 MHz
• ARM™ Cortex-M4, 32-bit CPU
– Supports ARMv7 - ISA
– 16 KB Instruction cache, 16 KB Data cache
– 64 KB Tightly-Coupled Memory (TCM)
– Single Precision FPU
– NVIC Interrupts Controller
– 1.25 DMIPS per MHz integer performance
– Up to 160 MHz
• I/O Processor
– ARM™ Cortex-M0+, 32-bit CPU
– Intelligent Stepper Motor Drive
• Memory subsystem
– System Memory Protection Unit
– 4 MB on-chip flash supported with the flash
controller
– 1 MB on-chip SRAM with ECC
– 1.3 MB on-chip Graphics SRAM with FlexECC
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator
– External 3.3 V input supply
– Option for direct, external supply of core voltage
– Low Voltage Detect (LVD) and High Voltage
Detect (HVD) on various supplies and regulators
SAC57D54H
• Debug functionality
– Run-time debug control of cores and visibility of
system resources using the Debug Access Port
(DAP)
– IEEE 1149.1/ IEEE 1149.7 System JTAG Controller
(SJTAG)
– Program and Data Trace support (16-bit data width)
implemented by the ARM Trace Port Interface Unit
(TPIU) Trace capture
• Timer
– Four 8-channel Flextimer modules (FTM)
– Two 4 channel System Timer Module (STM)
– Three Software WatchDog Timers (SWT)
– One 8 channel Periodic Interrupt Timer (PIT)
– Autonomous Real Time Counter (RTC)
• Analog
– 1 x 24 channel, 12-bit analog-to-digital converter
(ADC)
– 2 analog comparators (CMP)
• Security
– Cryptographic Services Engine (CSE)
• Safety
– ISO26262 ASIL-B compliance
– Password and Device Security (PASS) supporting
advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to
collect faults and issue interrupts
• Multiple operating modes
– Includes enhanced low power operation
• Memory interfaces
– 2 x Dual QuadSPI Serial flash controllers
– Supports SDR and DDR serial flash
– Support for 3.3 V Hyperflash (Spansion)
– DRAM controller supporting SDR and DDR2
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 kHz IRC (SIRC)
– 32 kHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Graphics interfaces
– Vivante GC355 GPU supporting OpenVG 1.1
– 2 x 2D-ACE Display Controllers (with inline Head-Up-Display warping)
– Digital RGB, TCON_0 (RSDS), TCON_1 and OpenLDI/LVDS output options
– Digital Video Input (VIU4)
– RLE Decoder for memory-memory decompression
– 40x4 segment LCD driver, reconfigurable as 38x6 or 36x8
• Cluster peripherals
– Sound Generator Module (SGM)
– 6 Stepper Motor Drivers with Stepper Stall Detect
• Communication
– Ethernet 10/100 + AVB (ENET)
– MLB50
– FlexCAN x 3
– DSPI x 5
– LINFlexD x 3 (1 x Master/Slave, 2 x Master only)
– I2C x 2
• eDMA controller with multiple transfer request sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flash programming
SAC57D54H, Rev. 7, 05/2017
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NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 5
Family comparison.............................................................................6
Ordering parts.....................................................................................8
3.1
3.2
4
Determining valid orderable parts ..........................................8
Ordering information ..............................................................8
6.2.5
6.3
6.2.4
6.2.2
6.2.3
Slow Oscillator (SXOSC) electrical specifications .. 32
Fast internal RC Oscillator (FIRC) electrical
specifications............................................................. 32
Slow internal RC oscillator (SIRC) electrical
specifications ............................................................ 32
PLL electrical specifications .................................... 33
General............................................................................................... 9
4.1
4.2
4.3
Absolute maximum ratings..................................................... 9
Recommended operating conditions....................................... 10
Voltage regulator electrical specifications.............................. 11
4.3.1
4.4
4.5
4.6
4.7
Decoupling capacitor values......................................12
Memory interfaces...................................................................34
6.3.1
Flash memory specifications..................................... 34
6.3.1.1
Flash memory program and erase
specifications......................................... 34
6.3.1.2
Flash memory Array Integrity and
Margin Read specifications................... 35
6.3.1.3
Flash memory module life
specifications......................................... 36
6.3.1.4
6.3.1.5
Data retention vs program/erase cycles. 36
Flash memory AC timing
specifications......................................... 37
6.3.1.6
Flash read wait state and address
pipeline control settings ........................ 38
6.3.2
QuadSPI AC specifications....................................... 38
6.3.2.1
6.3.2.2
6.3.2.3
6.3.3
SDR mode..............................................39
DDR mode............................................. 40
HyperFlash mode...................................42
Voltage monitor electrical specifications................................13
Power consumption................................................................. 14
Electrostatic discharge (ESD) specifications.......................... 15
Electromagnetic Compatibility (EMC) specifications............ 16
5
I/O parameters....................................................................................16
5.1
5.2
5.3
5.4
5.5
AC specifications @ 3.3 V range............................................16
DC electrical specifications @ 3.3 V range............................ 17
AC specifications @ 5 V range...............................................17
DC electrical specifications @ 5 V range............................... 18
DDR2 pads IO specifications..................................................19
5.5.1
DDR2 pads AC specifications @ 1.8V
VDDE_DDR..............................................................19
5.5.2
5.6
SSTL_18 Class II 1.8 V DDR2 DC specifications....20
SMC pads IO specifications....................................................21
5.6.1
SMC 5V pads IO specifications................................ 21
5.6.1.1
5.6.1.2
5.6.2
SMC 5V pads IO DC specifications...... 21
SMC 5V pads IO AC specifications...... 22
6.4
SDR AC specifications..............................................43
6.3.3.1
SDR DC specifications.......................... 45
6.3.4
DDR2 SDRAM AC specifications............................ 45
Communication modules.........................................................48
6.4.1
6.4.2
6.4.3
SPI electrical specifications.......................................48
Ethernet AC specifications........................................ 54
MediaLB (MLB) electrical specifications.................55
6.4.3.1
MLB 3-wire interface DC
specifications......................................... 55
6.4.3.2
MLB 3-wire interface electrical
specifications......................................... 56
SMC 3.3 V pads IO specifications............................ 22
5.6.2.1
5.6.2.2
SMC 3.3 V pads IO DC specifications.. 22
SMC 3.3 V pads IO AC specifications.. 22
5.7
5.8
5.9
RSDS pads electrical specifications........................................23
LVDS pads electrical specifications....................................... 25
Functional reset pad electrical specifications..........................26
5.10 PORST electrical specifications..............................................26
6
Peripheral operating requirements and behaviors.............................. 27
6.1
Analog modules.......................................................................27
6.1.1
6.1.2
6.2
ADC electrical specifications.................................... 27
Analog Comparator (CMP) electrical specifications 29
6.5
Display modules......................................................................58
6.5.1
6.5.2
LCD driver electrical specifications.......................... 58
2D-ACE electrical specifications.............................. 58
6.5.2.1
Interface to TFT LCD Panels (2D-
ACE)...................................................... 58
Clocks and PLL interfaces modules........................................30
6.2.1
Fast Oscillator (FXOSC) electrical specifications.... 30
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
3
6.5.2.2
Interface to TFT LCD Panels—pixel
level timings...........................................59
6.7.1
6.7.2
6.7.3
6.7.4
7
JTAG interface timing .............................................. 65
Debug trace timing specifications............................. 67
Wakeup Unit (WKPU) AC specifications.................68
External interrupt timing (IRQ pin)...........................68
6.5.2.3
Interface to TFT LCD panels—access
level........................................................61
6.5.3
6.5.4
Video input unit (VIU4) electrical specifications..... 62
TCON electrical specifications..................................63
6.5.4.1
6.5.4.2
TCON RSDS electrical specifications...63
TCON TTL electrical specifications......63
Thermal attributes.............................................................................. 69
7.1
Thermal attributes................................................................... 69
8
Dimensions.........................................................................................71
8.1
Obtaining package dimensions ...............................................71
6.6
Motor control modules............................................................ 64
6.6.1
Stepper Stall Detect (SSD) specifications................. 64
9
Pinouts................................................................................................71
9.1
Package pinouts and signal descriptions................................. 71
6.7
Debug specifications............................................................... 65
10 Revision History.................................................................................71
SAC57D54H, Rev. 7, 05/2017
4
NXP Semiconductors
Block diagram
1 Block diagram
RSDS / RGB
RGB
LVDS
System Modules
NVIC
GIC
I/O Ctrl
Reset Ctrl
INT Router
Temp Sensor
MBIST
64KB
TCM
FPU
16KB L1 16KB L1
D-Cache I-Cache
Code
System
DMAMUX (64:16)
16ch eDMA_0
16ch eDMA_1
SECURITY
(CSE)
FPU
32KB L1 32KB L1
D-Cache I-Cache
Tiny UI
2D-ACE
2D-ACE
HUD Warping
AXI
AHB
AHB
AHB
AHB
AHB
AHB
AHB
AXI
64
64
64
32
32
64
64
64
64
64
64
64
64
Clocking
4-40MHz/32KHz
XOSC
System Bus
Memory Protection
AHB
64
AHB
64
AHB
64
AHB
64
AHB
64
AHB
64
AXI
Pixel
Converter
64
AHB
64
AHB
64
AHB
64
AHB
64
AXI
64 AHB 64
16MHz/128KHz
IRC
PLLs
Clock Monitor
RLE
Decoder
QuadSPI
Power
LVD / HVD
Low Power Ctrl
2 - 4MB
Flash memory (ECC)
EE Emulation
OTP
1.3MB
GRAM
(FlexECC)
Boot ROM
QuadSPI
Flash memory BIU
512kB
System
SRAM (ECC)
512kB
System
SRAM (ECC)
Port Splitter
DRAM Controller
16/32-bit
SDR
DDR2
AIPS
CA5 GIC
CM4 NVIC
Debug
SJTAG
Autonomous RTC
Timer/PWM (8ch)
Timer/PWM (8ch)
Timer/PWM (8ch)
Timer/PWM (8ch)
12-bit ADC (24)
SMC & SSD (6)
UART/LIN (3)
TPIU
IOP
FlexCAN (3)
STM (4CH)
DSPI (5)
SWT (3)
CMP (2)
I2C (2)
CRC
LCD
4k and 2k ETBs
SGM (I2S)
PIT (8CH)
SEMA42
ARM
CortexM0+
32k SRAM
(ECC)
Interrupt
Router
Peripheral
Interrupts
Figure 1. High level block diagram
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
5
AHB
32
AXI
AXI
AXI
AXI
MLB50
NEON
VIU4
OpenVG 1.1
ENET-AVB
ARM
Cortex M4
ARM
Cortex A5
RSDS
OpenLDI/LVDS
GC355
GPU
TCON_0
TCON_1
LDB
DAP
