SB-36200IX
Make sure the next
Card you purchase
has...
®
COMBINATION S/R-TO-DIGITAL AND
DIGITAL-TO-S/R PCI BUS CONVERTER CARD
FEATURES
•
Includes Four RD-19230 Converters
•
Software Programmable: Resolution
(10, 12, 14, or 16 Bit) and Bandwidth
(Low: 15/45 Hz, High: 100/300 Hz)
•
Input Amplitude: 2 V
rms(
L-L
)
,
11.8 V
rms(
L-L
)
, or 90 V
rms(
L-L
)
•
Optional Two Channels of Digital-to-
Synchro/Resolver Conversion
•
Dynamic Rotation
•
Two-Speed Measurement and
Simulation
•
On-Board Programmable Oscillator
with Optional 1.5 VA Drive
DESCRIPTION
The SB-36200IX is a PCI bus card that contains four channels of fully
independent Synchro/Resolver-to-Digital (S/R-D) conversion and up
to two channels of Digital-to-Synchro/Resolver (D-S/R) conversion.
The SB-36200IX card has an on-board programmable oscillator to
support voltage ranges of 3.4 Vrms, 26 Vrms or 115 Vrms from 57 to
7kHz (See ordering information for range and output drive selec-
tions).
The resolution (10, 12, 14 or 16 bit) and bandwidth low (15 Hz/45 Hz)
or high (100 Hz/300 Hz) are software programmable. Each channel
has an independent signal and reference input. The standard inputs
are solid state. The signal connections are provided through a 68-pin
mini D-type connector (P1).
The SB-36200IX PCI card has up to two channels of fully independ-
ent Digital-to-Synchro or Digital-to-Resolver conversion. For each
channel the conversion process is implemented using DDC D/S or
D/R converters DSC-11520, DSC-11524 or DR-11525 (See hybrid
data sheets for output characteristics).
DIGITAL-TO-SYNCHRO/RESOLVER
SYNCHRO/RESOLVER-TO-DIGITAL
•
DLL’s and Libraries for Windows®
9x/2000/XP Windows NT®, Linux,
,
and LabVIEW™, (dataSIMS Support)
•
0° to 70° C Standard Operating
Temperature
•
Velocity Output
•
Output Amplitudes:
11.8 V
rms(
L-L
)
Synchro,
11.8 V
rms(
L-L
)
Resolver,
2 V
rms(
L-L
)
Direct
•
Output Voltages can be Scaled Lower
•
A quad B Encoder Emulation
APPLICATIONS
The SB-36200IX has been designed for modern, high performance
industrial and military position feedback, control, and test systems.
Typical motion feedback applications include motor control, machine tool
control, antenna control, robotics, and process control systems. The SB-
36200IX is supplied with a Windows GUI which creates a simple graphi-
cal interface to analyze or simulate position information, direction and BIT.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2001 Data Device Corporation
Data Device Corporation
www.ddc-web.com
THIN-FILM
RESISTOR
NETWORK
TRANSFORMER
(OPTIONAL)
AMPLIFIER
OSCILLATOR
RH OUT
RL OUT
Input
SIN
COS
RH
RL
P1
S1
S2
S3
S4
RH
RL
Channels 1- 4
INPUT
SCALING
RD-19230
MONOLITHIC
RESOLVER
-TO-
DIGITAL
CONVERTER
S1
S2
S3
S4
RH
RL
PCI BUS
2
Output Channels 1- 2
S1
(Optional)
D/S or D/R
HYBRID
CONVERTER
S2
S3
S4
INTERNAL
REGISTER
DATA
RH
RL
REFERENCE
SCALING
Output
Channels 1- 4
ADDRESS
DECODER
ADDRESS
A
B
ZIP
VEL
SB-36200IX
J-11/05-0
FIGURE 1. SB-36200IX BLOCK DIAGRAM
TABLE 1. SB-36200IX SPECIFICATIONS
(PER CHANNEL)
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation and
10% harmonic distortion.
PARAMETER
RESOLUTION
UNIT
Bits
VALUE
10, 12, 14, or 16 programmable
Input Frequency
47 -1k
1k - 4k
4k - 7k
(NOTE 2)
TABLE 1. SB-36200IX SPECIFICATIONS (CONT.)
(PER CHANNEL)
These specifications apply over the rated power supply, temperature,
and reference frequency ranges; 10% signal amplitude variation and
10% harmonic distortion.
PARAMETER
DIGITAL OUTPUTS (S/R-D)
A, B, Zero Index Pulse(ZIP)
Drive Capability
UNIT
VALUE
50 Pf+
Logic 0: 1 TTL load, 1.6 mA
at 0.4 V max.
Logic 1: 10 TTL loads, -0.4 mA
at 2.8 V min.
Logic 0: 100 mV max. driving
CMOS
Logic 1: +5 V supply minus
100mV min. driving CMOS
Natural binary angle, parallel
positive logic CMOS and TTL
compatible. Inputs are CMOS
transient protected.
Logic 0 = 0 to +1 V
Logic 1 = 2.2 V to +5 V
20 max to GND (bits 1 - 16)
20 max to +5 V (/LL, /LM, /LA)
(See timing diagrams
in D-S/R data sheets)
+5
0.5 with oscillator, no load,
4 channels (worst case)
1.3 with oscillator, no load,
2 channels (worst case)
0 to +70
-40 to +85
7.7 x 4.2 x 0.91
(195.6 x 106.7 x 23.1)
ACCURACY (S/R-D)
RD-19230 (1 Min + 1 LSB) Minutes 1 + 1 LSB 1 + 1 LSB 2 + 1 LSB
ACCURACY (D-S/R)
DSC-11520-305
DR-11525-305
DSC-11524-304
OSCILLATOR
Carrier Frequency
Voltage Range
Drive
SIGNAL INPUT (S/R-D)
(Synchro Type)
• Zin line-to-line
• Zin each line-to-ground
(Resolver Type)
• Zin single ended
• Zin differential
Common-mode Range
R/D REFERENCE INPUT
Voltage Range
Input Impedance
• Single Ended
• Differential
D/R REFERENCE INPUT
(NOTE 3)
Input Impedance
• Single Ended
• Differential
D - S/R DRIVE
DSC-11520
DSC-11524
DR-11525
DYNAMIC
ROTATION
Vrms
L-L
Ohms
Ohms
Vrms
L-L
Ohms
Ohms
V
Vrms
Vrms
kOhms
kOhms
Vrms
11.8
52k
35k
11.8
70k
140k
30 max.
4.4
2 - 40
200
400
4.4
After Set into A quad mode
Minutes
Minutes
Minutes
1
1
2
For frequencies higher than
1 kHz use the DR-11525
and refer to the converter
data sheet specifications.
(Option X) (Option A) (Option B)
Hz
Vrms
mA. max
360 - 7k
0 - 3.4
300
360 - 7k
0 - 26
60
Solid State
90
195k
130k
—
—
—
—
26
12 - 40
100
200
26
—
—
—
2V
rms
direct
10M || 20pF
(NOTE 1)
N/A
N/A
115
62 - 130
600
1200
115
57 - 440
0 - 115
13
DIGITAL INPUTS (D-S/R)
Logic Type
µA
µA
POWER SUPPLY (NOTE 5)
Voltage
S/R-D Current
D-S/R Current
TEMPERATURE RANGE
Operating (SB-3620XIX-3XX)
Storage
PHYSICAL
CHARACTERISTICS
Vdc
Amax
Amax
°C
°C
in.
(mm.)
kOhms
kOhms
mA(rms)
mA(rms)
mA(rms)
45
90
25
50
2 max
15 max
2 max
125
250
at 12 bit resolution (0.03 to 2014)
rps
min/max at 16 bit resolution (0.05 to 125)
NOTES: 1. || = “in parallel with.”
2. If the frequency is between 47 and 1 kHz, then there
will be 1 LSB jitter in the S/R-D.
3. Reference input voltage to D-S/R converter must be
90/26/4.4 Vrms prorated output.
4. See specific converter data sheets for further specifications.
5. Requires a 5V PCI card slot, will not operate on a 3.3V PCI
slot.
TABLE 2. DYNAMIC CHARACTERISTICS (S/R-D)
TYPE
Resolution (bits)
Low
Bandwidth (Hz)
High
Tracking Rate (rps)
32
45
8
.5
**
2
2
**
.5
8
300
320
80
**
20
.2
**
5
.8
60 HZ NOMINAL
10
*
12
*
14
15
16
400 HZ NOMINAL
10
*
12
*
14
16
TABLE 3. VELOCITY CHARACTERISTICS (S/R-D)
PARAMETER
POLARITY
Voltage Range
VOLTAGE SCALING
(resolution dependent)
SCALE FACTOR
Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
UNITS
V
Volts/rps
%
PPM / deg C
%
% output
mV
uV / deg C
k Ohms
TYPICAL
4.0
Typical Tracking Rate
(See TABLE 2)
10
100
1
0.5
5
15
20 (max.)
200 (max.)
2 (max.)
1 (max.)
15 (max.)
30 (max.)
10 (min.)
MAX. / MIN.
100
Scale Factor (Volts/rps) .125
.0125 .05
* Not Recommended - Low bandwidths in low resolutions may induce spin around
and the part will not settle.
**High bandwidths in high resolutions may be used with carrier frequencies above
1.5 kHz.
Data Device Corporation
www.ddc-web.com
3
SB-36200IX
J-11/05-0
SYNTHESIZED REFERENCE
The RD-19230 input converters contain a synthesized reference,
which eliminates errors due to phase shift between the reference
and the signal inputs up to 45°. Quadrature voltages in a resolver
or synchro are by definition the resulting 90° fundamental signal
in the nulled out error voltage (e) in the converter. Due to the
inductive nature of resolvers and synchros, their output signals
lead the reference input signal (RH and RL). When an uncom-
pensated reference signal is used to demodulate the control
transformer’s output, quadrature voltages are not completely
eliminated. Therefore this is the perfect solution to combat phase
shift error to 45°.
ON BOARD INTERNAL REFERENCE OSCILLATOR
The on board oscillator is available with an optional 1.5VA drive.
This on board reference oscillator may be looped back to each
input channel’s independent reference input. Frequency is pro-
grammable, and voltage is programmable per the oscillator volt-
age range selected.
INTERNAL INCREMENTAL OPTICAL ENCODER
EMULATION
The card can be programmed to encoder emulation mode (Refer
to FIGURES 2 and 3). These outputs are available on the P1
connector A, B & ZIP (which is the zero index pulse). The timing
of the A, B output is dependent on the rate of change of the syn-
chro/resolver position (rps or degrees per second) and the
encoder resolution latched into the converter.
BUILT-IN-TEST
Built-In-Test (BIT) will flag Loss-Of-Signal (LOS) and Loss-Of-
Reference (LOR) fault conditions. Also, excessive error is detect-
ed by monitoring the demodulator output, which is proportional
to the difference between the analog input and the digital output.
When it exceeds approximately 100 LSB's (in the selected reso-
lution), the BIT will be asserted. This condition can occur any
time the analog input changes at a rate in excess of the maxi-
mum tracking rate. During power up, the converter may see a
large difference between the sin/cos inputs and the digital output
angle held in its counter. BIT will be asserted until the converter
settles within 100 LSB's of the final result.
RD-19230
DUAL BANDWIDTHS
The user can program bandwidth for each input channel inde-
pendently through software. The Low bandwidth card can be pro-
grammed for bandwidths of either 15 or 45Hz. The High band-
width card can be programmed for bandwidths of either 100 or
300Hz.
1
0
1
2
1
4
1
6
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BIT 16 LSB
A
B
FIGURE 2. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
B(X- or LSB & LSB+1)
2t
A (LSB+1)
ZIP (NRP)
t
0
T
359.95
FIGURE 3. INCREMENTAL ENCODER EMULATION
Data Device Corporation
www.ddc-web.com
SB-36200IX
J-11/05-0
4
S/R SIGNAL INPUT CONFIGURATION
Configuration for the synchro/resolver inputs is accomplished by
the use of specific thin-film resistor networks installed on the
card. These networks also scale the input voltage to the convert-
er for a choice of either 2V L-L, 11.8V L-L, or 90V L-L
synchro/resolver full scale input signal.
TABLE 4. SIGNAL INPUT CONFIGURATION
INPUT TYPE
2V Direct
11.8V Resolver
11.8V Synchro
THIN FILM RESISTOR NETWORK
DDC - 55688-1
DDC - 49530
DDC - 49530
DDC - 49590, 49450*
LOCATION
Lower Sockets
Lower Sockets
Upper Sockets
Upper Sockets
SYNCHRO/RESOLVER-TO-DIGITAL
Refer to FIGURE 4 for socket locations on the card. TABLE 4 lists
the resistor network and location for each input option.
90V Synchro
*DDC-49450 is a ceramic alternate of the DDC-49590
Synchro
Pin 1
Pin 1
Resolver / Direct
C92
+
C91
C90
+
+
C57
U14
U9
+
+
+
C93
C54
T1
U15
R117
R116
R136
R135
W96
R58
TB1
TB3
TB7
TB6
TB2
TB5
TB4
W95
R59
C47
C75
S4
P1
C164
S3
S2
C123
S1
U10
+
C61
U3
U27
U22
C124
C161
C14
C122 C127
U29
C154 C165
C152
C163
U20
+
C71
+
C69
+
C74
+
C72
C70
U2
U13
C73
P3
C1
C7
U4
P4
U11
U12
+
C50
C52
C2
FIGURE 4. INPUT SIGNAL CONFIGURATION
Data Device Corporation
www.ddc-web.com
5
C51
+
C155
U26
U25
C125
U19
U18
C59
+
C65
SB-36200IX
J-11/05-0
传感器
