SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA)
encoder/decoder
Rev. 05 — 10 May 2004
Product data
1. Description
The SC16C554/554D is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel or Motorola interface.
The SC16C554/554D is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control
registers enables the added features of the SC16C554/554D. Some of these added
features are the 16-byte receive and transmit FIFOs, automatic hardware or software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency while in FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C554/554D also provides DMA mode data transfers through FIFO
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide
the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back
capability allows on-board diagnostics.
The SC16C554/554D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.
2. Features
s
5 V, 3.3 V and 2.5 V operation
s
Industrial temperature range
s
The SC16C554/554D is pin compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554
s
Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s
16-byte transmit FIFO
s
16-byte receive FIFO with error flags
s
Automatic software/hardware flow control
s
Programmable Xon/Xoff characters
s
Software selectable Baud Rate Generator
s
Four selectable Receive FIFO interrupt trigger levels
s
Standard modem interface or infrared IrDA encoder/decoder interface
s
Sleep mode
s
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
s
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
s
Fully programmable character formatting:
x
5, 6, 7, or 8-bit characters
x
Even, Odd, or No-Parity formats
x
1, 1
1
⁄
2
, or 2-stop bit
x
Baud generation (DC to 5 Mbit/s)
s
False start-bit detection
s
Complete status reporting capabilities
s
3-State output TTL drive capabilities for bi-directional data bus and control bus
s
Line Break generation and detection
s
Internal diagnostic capabilities:
x
Loop-back controls for communications link fault isolation
s
Prioritized interrupt system controls
s
Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
3. Ordering information
Table 1:
Ordering information
Package
Name
SC16C554DIA68
SC16C554DIB64
SC16C554IB64
SC16C554IB80
PLCC68
LQFP64
LQFP64
LQFP80
Description
plastic leaded chip carrier; 68 leads
plastic low profile quad flat package; 64 leads; body 10
×
10
×
1.4 mm
plastic low profile quad flat package; 64 leads; body 10
×
10
×
1.4 mm
plastic low profile quad flat package; 80 leads; body 12
×
12
×
1.4 mm
Version
SOT188-2
SOT314-2
SOT314-2
SOT315-1
Type number
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 05 — 10 May 2004
2 of 55
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
4. Block diagram
SC16C554/554D
TRANSMIT
FIFO
REGISTERS
D0–D7
IOR
IOW
RESET
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TXA-TXD
IR
ENCODER
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA-RXD
A0–A2
CSA-CSD
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
16/68
DTRA-DTRD
RTSA-RTSD
INTA-INTD
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
INTSEL
MODEM
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
CTSA-CTSD
RIA-RID
CDA-CDD
DSRA-DSRD
002aaa168
XTAL1
XTAL2
CLKSEL
Fig 1. SC16C554/554D block diagram (16 mode).
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 05 — 10 May 2004
3 of 55
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
SC16C554/554D
TRANSMIT
FIFO
REGISTERS
D0–D7
R/W
RESET
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TXA-TXD
IR
ENCODER
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA-RXD
A0–A4
CS
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
16/68
DTRA-DTRD
RTSA-RTSD
MODEM
CONTROL
LOGIC
IRQ
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
CTSA-CTSD
RIA-RID
CDA-CDD
DSRA-DSRD
002aaa343
XTAL1
XTAL2
CLKSEL
Fig 2. SC16C554/554D block diagram (68 mode).
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 05 — 10 May 2004
4 of 55
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
5. Pinning information
5.1 Pinning
5.1.1
PLCC68
65 INTSEL
GND
61 CDD
CDA
64 VCC
63 RXD
RXA
62 RID
RIA
D7
D6
D5
D4
D3
68 D2
67 D1
66 D0
9
8
7
6
5
4
3
2
1
DSRA 10
CTSA 11
DTRA 12
VCC 13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
60 DSRD
59 CTSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
SC16C554DIA68
16 MODE
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 VCC
46 DTRC
45 CTSC
44 DSRC
CDB 27
RIB 28
RXB 29
VCC 30
n.c. 31
A2 32
A1 33
A0 34
XTAL1 35
XTAL2 36
RESET 37
RXRDY 38
TXRDY 39
GND 40
RXC 41
RIC 42
CDC 43
002aaa166
Fig 3. PLCC68 pin configuration (16 mode).
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 05 — 10 May 2004
5 of 55
