SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte
FIFOs
Rev. 04 — 6 October 2008
Product data sheet
1. General description
The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V). The SC16C754B offers enhanced features. It has a Transmission Control
Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during
hardware and software flow control. With the FIFO Ready (FIFO Rdy) register, the
software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status
registers provide the user with error indications, operational status, and modem interface
control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed
to interrupt at different trigger levels. The UART generates its own desired baud rate
based upon a programmable divisor and its input clock. It can transmit even, odd, or no
parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors,
FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART
also contains a software interface for modem control operations, and has software flow
control and hardware flow control capabilities.
The SC16C754B is available in plastic LQFP64, LQFP80 and PLCC68 packages.
2. Features
I
4 channel UART
I
5 V, 3.3 V and 2.5 V operation
I
Pin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional
enhancements, and software compatible with TL16C754
I
Up to 5 Mbit/s data rate (at 3.3 V and 5 V; at 2.5 V maximum data rate is 3 Mbit/s)
I
5 V tolerant on input only pins
1
I
64-byte transmit FIFO
I
64-byte receive FIFO with error flags
I
Industrial temperature range (−40
°C
to +85
°C)
I
Programmable and selectable transmit and receive FIFO trigger levels for DMA and
interrupt generation
1.
For data bus pins D7 to D0, see
Table 24 “Limiting values”.
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
I
Software (Xon/Xoff)/hardware (RTS/CTS) flow control
N
Programmable Xon/Xoff characters
N
Programmable auto-RTS and auto-CTS
I
Optional data flow resume by Xon any character
I
DMA signalling capability for both received and transmitted data
I
Supports 5 V, 3.3 V and 2.5 V operation
I
Software selectable baud rate generator
I
Prescaler provides additional divide-by-4 function
I
Fast data bus access time
I
Programmable Sleep mode
I
Programmable serial interface characteristics
N
5, 6, 7, or 8-bit characters
N
Even, odd, or no-parity bit generation and detection
N
1, 1.5, or 2 stop bit generation
I
False start bit detection
I
Complete status reporting capabilities in both normal and Sleep mode
I
Line break generation and detection
I
Internal test and loopback capabilities
I
Fully prioritized interrupt system controls
I
Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)
I
Sleep mode
3. Ordering information
Table 1.
Ordering information
Package
Name
SC16C754BIBM
SC16C754BIB80
SC16C754BIA68
LQFP64
LQFP80
PLCC68
Description
plastic low profile quad flat package; 64 leads; body 7
×
7
×
1.4 mm
plastic low profile quad flat package; 80 leads; body 12
×
12
×
1.4 mm
plastic leaded chip carrier; 68 leads
Version
SOT414-1
SOT315-1
SOT188-2
Type number
SC16C754B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
2 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
4. Block diagram
SC16C754B
TRANSMIT
FIFO
REGISTERS
TRANSMIT
SHIFT
REGISTER
TXA to TXD
D0 to D7
IOR
IOW
RESET
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA to RXD
A0 to A2
CSA to CSD
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
DTRA to DTRD
RTSA to RTSD
INTA to INTD
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
CTSA to CTSD
RIA to RID
CDA to CDD
DSRA to DSRD
INTSEL
002aaa866
XTAL1 XTAL2
CLKSEL
Fig 1.
Block diagram of SC16C754B
SC16C754B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
3 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5. Pinning information
5.1 Pinning
61 GND
49 CDD
48 DSRD
47 CTSD
46 DTRD
45 GND
44 RTSD
43 INTD
42 CSD
41 TXD
40 IOR
39 TXC
38 CSC
37 INTC
36 RTSC
35 V
CC
34 DTRC
33 CTSC
DSRB 17
CDB 18
RIB 19
RXB 20
V
CC
21
A2 22
A1 23
A0 24
XTAL1 25
XTAL2 26
RESET 27
GND 28
RXC 29
RIC 30
CDC 31
DSRC 32
002aab564
64 CDA
51 RXD
62 RXA
52 V
CC
DSRA
CTSA
DTRA
V
CC
RTSA
INTA
CSA
TXA
IOW
1
2
3
4
5
6
7
8
9
SC16C754BIBM
TXB 10
CSB 11
INTB 12
RTSB 13
GND 14
DTRB 15
CTSB 16
Fig 2.
Pin configuration for LQFP64
SC16C754B_4
50 RID
63 RIA
60 D7
59 D6
58 D5
57 D4
56 D3
55 D2
54 D1
53 D0
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
4 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
67 INTSEL
76 GND
63 CDD
79 CDA
65 RXD
77 RXA
66 V
CC
64 RID
78 RIA
80 n.c.
62 n.c.
n.c.
n.c.
DSRA
CTSA
DTRA
V
CC
RTSA
INTA
CSA
1
2
3
4
5
6
7
8
9
61 n.c.
75 D7
74 D6
73 D5
72 D4
71 D3
70 D2
69 D1
68 D0
60 n.c.
59 DSRD
58 CTSD
57 DTRD
56 GND
55 RTSD
54 INTD
53 CSD
52 TXD
51 IOR
50 TXC
49 CSC
48 INTC
47 RTSC
46 V
CC
45 DTRC
44 CTSC
43 DSRC
42 n.c.
41 n.c.
TXA 10
IOW 11
TXB 12
CSB 13
INTB 14
RTSB 15
GND 16
DTRB 17
CTSB 18
DSRB 19
n.c. 20
SC16C754BIB80
n.c. 21
n.c. 22
CDB 23
RIB 24
RXB 25
CLKSEL 26
n.c. 27
A2 28
A1 29
A0 30
XTAL1 31
XTAL2 32
RESET 33
RXRDY 34
TXRDY 35
GND 36
RXC 37
RIC 38
CDC 39
n.c. 40
002aaa867
Fig 3.
Pin configuration for LQFP80
SC16C754B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
5 of 51
FPGA/CPLD
