SC16C850L
1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs,
infrared (IrDA) and 16 mode or 68 mode parallel bus interface
Rev. 5 — 1 February 2011
Product data sheet
1. General description
The SC16C850L is a 1.8 V, low power, single channel Universal Asynchronous Receiver
and Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. The SC16C850L is functionally (software) compatible with the
SC16C650B. SC16C850L can be programmed to operate in extended mode (see
Section 6.2)
where additional advanced UART features are available. The SC16C850L
UART provides enhanced UART functions with 128-byte FIFOs, modem control interface,
and IrDA encoder/decoder. On-board status registers provide the user with error
indications and operational status. System interrupts and modem control features may be
tailored by software to meet specific user requirements. An internal loopback capability
allows on-board diagnostics.
The SC16C850LIBS with Intel (16 mode) or Motorola (68 mode) bus host interface
operates at 1.8 V and is available in a very small (Micro-UART) HVQFN32 package.
The SC16C850LIET with Intel (16 mode) bus host interface operates at 1.8 V and is
available in a very small TFBGA36 package.
2. Features and benefits
Single channel high performance UART
Intel or Motorola bus interface selectable using 16/68 pin
1.8 V operation
Up to 5 Mbit/s data rate
128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
128-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
128 programmable Receive and Transmit FIFO interrupt trigger levels
128 Receive and Transmit FIFO reporting levels (level counters)
Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
Industrial temperature range (40
C
to +85
C)
128 hardware and software trigger levels
Automatic 9-bit mode (RS-485) address detection
Automatic RS-485 driver turn-around with programmable delay
UART software reset
High resolution clock prescaler, from 0 to 15 with granularity of
1
16
to allow
non-standard UART clock to be used
Programmable Xon/Xoff characters
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Software selectable baud rate generator
Support IrDA version 1.0 (up to 115.2 kbit/s)
Standard modem interface or infrared IrDA encoder/decoder interface
Enhanced Sleep mode and low power feature
Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
Independent transmitter and receiver enable/disable
Pb-free, RoHS compliant package offered
3. Ordering information
Table 1.
Ordering information
Package
Name
SC16C850LIBS
SC16C850LIET
HVQFN32
TFBGA36
Description
Version
plastic thermal enhanced very thin quad flat package; SOT617-1
no leads; 32 terminals; body 5
5
0.85 mm
plastic thin fine-pitch ball grid array package; 36 balls; SOT912-1
body 3.5
3.5
0.8 mm
Type number
SC16C850L
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 1 February 2011
2 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
4. Block diagram
SC16C850L
TRANSMIT
FIFO
REGISTER
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
IR
ENCODER
TRANSMIT
SHIFT
REGISTER
TX
D0 to D7
IOR
IOW
RESET
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RX
A0 to A2
CS
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
LOWPWR
POWER-DOWN
CONTROL
DTR
RTS
MODEM
CONTROL
LOGIC
INT
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
CTS
RI
CD
DSR
002aac416
XTAL1
XTAL2
Fig 1. Block diagram of SC16C850L (16 mode)
SC16C850L
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 1 February 2011
3 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
SC16C850L
TRANSMIT
FIFO
REGISTER
D0 to D7
R/W
RESET
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
IR
ENCODER
TRANSMIT
SHIFT
REGISTER
TX
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RX
A0 to A2
CS
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
LOWPWR
POWER-DOWN
CONTROL
DTR
RTS
MODEM
CONTROL
LOGIC
IRQ
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
CTS
RI
CD
DSR
002aac417
XTAL1
XTAL2
Fig 2. Block diagram of SC16C850L (68 mode)
SC16C850L
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 1 February 2011
4 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
5. Pinning information
5.1 Pinning
ball A1
index area
1
A
B
C
D
E
F
002aac418
SC16C850LIET
2
3
4
5
6
Transparent top view
Fig 3. Pin configuration for TFBGA36
1
A
B
C
D
E
F
V
DD
A2
A0
INT
DTR
RESET
2
n.c.
n.c.
V
SS
RTS
n.c.
DSR
3
IOR
n.c.
A1
CTS
CD
RI
4
n.c.
IOW
V
SS
V
DD
D1
D0
5
XTAL2
LOWPWR
TX
D7
D3
D2
6
XTAL1
CS
RX
D6
D5
D4
002aac421
Transparent top view.
Fig 4. Ball mapping for TFBGA36
SC16C850L
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 1 February 2011
5 of 55
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