SC16IS741
Single UART with I
2
C-bus/SPI interface, 64 bytes of transmit
and receive FIFOs, IrDA SIR built-in support
Rev. 01 — 29 April 2010
Product data sheet
1. General description
The SC16IS741 is a slave I
2
C-bus/SPI interface to a single-channel high performance
UART. It offers data rates up to 5 Mbit/s and guarantees low operating and sleeping
current. The device comes in the TSSOP16 package, which makes it ideally suitable for
handheld, battery operated applications. This device enables seamless protocol
conversion from I
2
C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.
The SC16IS741’s internal register set is backward-compatible with the widely used and
widely popular 16C450. This allows the software to be easily written or ported from
another platform.
The SC16IS741 also provides additional advanced features such as auto hardware and
software flow control, automatic RS-485 support, and software reset. This allows the
software to reset the UART at any moment, independent of the hardware reset signal.
2. Features
2.1 General features
Single full-duplex UART
Selectable I
2
C-bus or SPI interface
3.3 V or 2.5 V operation
Industrial temperature range:
−40 °C
to +95
°C
64 bytes FIFO (transmitter and receiver)
Fully compatible with industrial standard 16C450 and equivalent
Baud rates up to 5 Mbit/s in 16× clock mode
Auto hardware flow control using RTS/CTS
Auto software flow control with programmable Xon/Xoff characters
Single or double Xon/Xoff characters
Automatic RS-485 support (automatic slave address detection)
RS-485 driver direction control via RTS signal
RS-485 driver direction control inversion
Built-in IrDA encoder and decoder interface
Software reset
Transmitter and receiver can be enabled/disabled independent of each other
Receive and Transmit FIFO levels
Programmable special character detection
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Fully programmable character formatting
5-bit, 6-bit, 7-bit or 8-bit character
Even, odd, or no parity
1, 1
1
⁄
2
, or 2 stop bits
Line break generation and detection
Internal Loopback mode
Sleep current less than 30
μA
at 3.3 V
Industrial and commercial temperature ranges
Available in the TSSOP16 package
2.2 I
2
C-bus features
Noise filter on SCL/SDA inputs
400 kbit/s maximum speed
Compliant with I
2
C-bus fast speed
Slave mode only
2.3 SPI features
Slave mode only
SPI Mode 0
3. Applications
Factory automation and process control
Portable and battery operated devices
Cellular data devices
4. Ordering information
Table 1.
Ordering information
Package
Name
SC16IS741IPW
TSSOP16
Description
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT403-1
Type number
SC16IS741_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
2 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
5. Block diagram
V
DD
SC16IS741
RESET
SCL
SDA
A0
A1
IRQ
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)
I
2
C-BUS
16C450
COMPATIBLE
REGISTER
SETS
TX
RX
RTS
CTS
V
DD
V
DD
I2C/SPI
XTAL1
XTAL2
V
SS
002aaf155
Fig 1.
Block diagram of SC16IS741 I
2
C-bus interface
V
DD
SC16IS741
RESET
SCLK
CS
SO
SI
IRQ
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)
SPI
16C450
COMPATIBLE
REGISTER
SETS
TX
RX
RTS
CTS
V
DD
I2C/SPI
XTAL1
XTAL2
V
SS
002aaf157
Fig 2.
Block diagram of SC16IS741 SPI interface
SC16IS741_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
3 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6. Pinning information
6.1 Pinning
V
DD
A0
A1
n.c.
SCL
SDA
IRQ
I2C
1
2
3
4
5
6
7
8
002aaf158
16 XTAL2
15 XTAL1
14 RESET
13 RX
12 TX
11 CTS
10 RTS
9
V
SS
V
DD
CS
SI
SO
SCLK
V
SS
IRQ
SPI
1
2
3
4
5
6
7
8
002aaf159
16 XTAL2
15 XTAL1
14 RESET
13 RX
12 TX
11 CTS
10 RTS
9
V
SS
SC16IS741IPW
SC16IS741IPW
a. I
2
C-bus interface
Fig 3.
Pin configuration for TSSOP16
b. SPI interface
6.2 Pin description
Table 2.
Symbol
V
DD
CS/A0
Pin description
Pin
1
2
Type Description
-
I
power supply
SPI chip select or I
2
C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip select
pin (Schmitt-trigger, active LOW). If I
2
C-bus configuration is selected
by I2C/SPI pin, this pin along with A1 pin allows user to change the
device’s base address.
SPI data input pin or I
2
C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data input pin.
If I
2
C-bus configuration is selected by I2C/SPI pin, this pin along with
A0 pin allows user to change the device’s base address. To select the
device address, please refer to
Table 28.
SPI data output pin. If SPI configuration is selected by I2C/SPI pin,
this is a 3-stateable output pin. If I
2
C-bus configuration is selected by
I2C/SPI pin, this pin function is undefined and must be left as n.c. (not
connected).
I
2
C-bus or SPI input clock.
I
2
C-bus data input/output, open-drain if I
2
C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this pin
is an undefined pin and must be connected to V
SS
.
Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register (IER).
Interrupt conditions include: change of state of the input pins, receiver
errors, available receiver buffer data, available transmit buffer space,
or when a modem status flag is detected. An external resistor (1 kΩ
for 3.3 V, 1.5 kΩ for 2.5 V) must be connected between this pin and
V
DD
.
I
2
C-bus or SPI interface select. I
2
C-bus interface is selected if this pin
is at logic HIGH. SPI interface is selected if this pin is at logic LOW.
SI/A1
3
I
SO
4
O
SCL/SCLK
SDA
5
6
I
I/O
IRQ
7
O
I2C/SPI
8
I
SC16IS741_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
4 of 52
NXP Semiconductors
SC16IS741
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Pin description
…continued
Pin
9
10
Type Description
-
O
ground
UART request to send (active LOW). A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing a
logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin is set to a
logic 1. This pin only affects the transmit and receive operations when
auto RTS function is enabled via the Enhanced Feature Register
(EFR[6]) for hardware flow control operation.
UART clear to send (active LOW). A logic 0 (LOW) on the CTS pin
indicates the modem or data set is ready to accept transmit data from
the SC16IS741. Status can be tested by reading MSR[4]. This pin
only affects the transmit and receive operations when auto CTS
function is enabled via the Enhanced Feature Register EFR[7] for
hardware flow control operation.
UART transmitter output. During the local Loopback mode, the TX
output pin is disabled and TX data is internally connected to the
UART RX input.
UART receiver input. During the local Loopback mode, the RX input
pin is disabled and TX data is connected to the UART RX input
internally.
device hardware reset (active LOW)
[1]
Crystal input or external clock input. Functions as a crystal input or as
an external clock input. A crystal can be connected between XTAL1
and XTAL2 to form an internal oscillator circuit (see
Figure 11).
Alternatively, an external clock can be connected to this pin.
Crystal output or clock output. (See also XTAL1.) XTAL2 is used as a
crystal oscillator output.
Table 2.
Symbol
V
SS
RTS
CTS
11
I
TX
12
O
RX
13
I
RESET
XTAL1
14
15
I
I
XTAL2
16
O
[1]
See
Section 7.4 “Hardware reset, Power-On Reset (POR) and software reset”
7. Functional description
The UART will perform serial-to-I
2
C conversion on data characters received from
peripheral devices or modems, and I
2
C-to-serial conversion on data characters
transmitted by the host. The complete status the SC16IS741 UART can be read at any
time during functional operation by the host.
The SC16IS741 can be placed in an alternate mode (FIFO mode) relieving the host of
excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 characters (including three additional
bits of error status per character for the receiver FIFO) and have selectable or
programmable trigger levels.
The SC16IS741 has selectable hardware flow control and software flow control. Hardware
flow control significantly reduces software overhead and increases system efficiency by
automatically controlling serial data flow using the RTS output and CTS input signals.
Software flow control automatically controls data flow by using programmable Xon/Xoff
characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2
16
– 1).
SC16IS741_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
5 of 52
DSP 与 ARM 处理器
