INTEGRATED CIRCUITS
SC26C562
CMOS dual universal serial
communications controller (CDUSCC)
Product data sheet
Supersedes data of 2004 Mar 29
2006 Aug 10
Philips
Semiconductors
Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
DESCRIPTION
The Philips Semiconductors SC26C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC26C562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The SC26C562 (CDUSCC) is (PIN) hardware and (REGISTER)
software compatible with the existing SCN26562 (DUSCC).
CDUSCC will automatically configure to the NMOS DUSCC register
map (default mode) on power-up.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides sixteen common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
CDUSCC well-suited for dual-speed channel applications. Data
rates up to 10 Mbit/s are supported.
The transmitter and receiver each contain a sixteen-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to sixteen characters
at a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
The SC26C562 CDUSCC is optimized to interface with processors
using a synchronous bus interface, such as the 8086, and iAPX86
family. For systems using an asynchronous bus, such as the 68000
and 68010, refer to the SC68C562 documentation.
Refer to the CMOS Dual Universal Serial Communication Controller
(CDUSCC) User’s Manual for a complete operational description.
•
Watchdog timer
•
0 to 10 Mbit/s data rate
•
Programmable bit rate for each receiver and transmitter selectable
from:
–
19 fixed rates: 50 to 64 kbaud
–
One user-defined rate derived from programmable
counter/timer
–
External 1X or 16X clock
–
Digital phase-locked loop
•
Parity and FCS (frame check sequence LRC or CRC) generation
and checking
•
Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
•
Programmable channel mode: full- or half-duplex, auto-echo, or
local loopback
•
Programmable data transfer mode: polled, interrupt, DMA, wait
•
DMA interface
–
Compatible with Synchronous and Asynchronous bus DMA
controllers
–
Half- or full-duplex operation
–
Single or dual address data transfers
–
Automatic frame termination on counter/ timer terminal count or
DMA DONE (EOPN)
•
Transmit path clear status
•
High speed data bus interface: 160 ns bus cycle
•
DPLL operation up to 312.5 kHz with internal clock
•
Interrupt capabilities
–
Vector output (fixed or modified by status)
–
Individual interrupt enable bits
–
Programmable internal priorities
–
Maskable interrupt conditions
–
80XX/X compatible
–
Bit rate generator
–
Event counter
–
Count received or transmitted characters
–
Delay generator
–
Automatic bit length measurement
•
Multi-function programmable 16-bit counter/timer
FEATURES
General Features
transmitter
•
Modem controls
–
RTS, CTS, DCD, and up to four general purpose I/O pins per
channel
–
CTS and DCD programmable auto-enables for Tx and Rx
–
Programmable interrupt on change of CTS or DCD
•
Dual full-duplex synchronous/ asynchronous receiver and
•
Multi-protocol operation
–
BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
–
COP: Single SYNC, dual SYNC, BiSYNC, DDCMP
–
ASYNC: 5-8 bits plus optional parity
•
On-chip oscillator for crystal
•
TTL compatible
•
Single +5 V power supply
•
Sixteen character receive and transmit FIFOs with interrupt
threshold control
•
FIFO’ed status bits
2006 Aug 10
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Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
Asynchronous Mode Features
•
Character length: 5 to 8 bits
•
Odd or even parity, no parity, or force parity
•
Up to two stop bits programmable in 1/16-bit increments
•
1X or 16X Rx and Tx clock factors
•
Parity, overrun and framing error detection
•
False start bit detection
•
Break generation with handshake for counting break characters
•
Detection of start and end of received break
•
Character compare with optional interrupt on match
•
Transmit and receive up to 10 Mbit/s at 1× or 1 Mbit/s at 16× data
rates
•
Extended address and control fields
•
Short frame rejection for receiver
•
Detection and notification of received end of message
•
CRC generation and checking
•
SDLC loop mode capability
Character-Oriented Protocols
Bit-Oriented Protocol
•
Character length: 5 to 8 bits
•
Detection and transmission of residual character: 0–7 bits
•
Automatic switch to programmed character length for I field
•
Zero insertion and deletion
•
Optional opening PAD transmission
•
Detection and generation of FLAG, ABORT, and IDLE bit patterns
•
Transmit 7 or 8 bit ABORT
•
Detection and generation of shared (single) FLAG between
frames
•
Character length: 5 to 8 bits
•
Odd or even parity, no parity, or force parity
•
LRC or CRC generation and checking
•
Optional opening PAD transmission
•
One or two SYN characters
•
External sync capability
•
SYN detection and optional stripping
•
SYN or MARK line-fill or underrun
•
Idle in MARK or SYNs
•
Parity, FCS, overrun and underrun error detection
•
Optional SYNC exclusion from FCS
•
BISYNC features
–
EBCDIC or ASCII header, text and control messages
–
SYN, DLE stripping
–
EOM (end of message) detection and transmission
–
Auto transparency mode switching
–
Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
–
Control character sequence detection for both transparent and
normal text
–
Parity generation for data and LRC characters
•
Detection of overlapping (shared zero) FLAGs
•
Idle in MARK or FLAGs
•
Secondary address recognition including group and global
address
•
Single- or dual-octet secondary address
ORDERING INFORMATION
T
amb
= 0
°
C to +70
°
C. Serial data rate = 10 Mbit/s maximum
Type number
Package
Name
SC26C562C1A
PLCC52
Description
plastic leaded chip carrier; 52 leads
Version
SOT238-2
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
T
amb
T
stg
V
CC
V
S
Storage temperature
Voltage from V
CC
to GND
3
Voltage from any pin to ground
3
PARAMETER
Operating ambient temperature
2
RATING
0 to +70
–65 to +150
–0.5 to +7.0
–0.5 to V
CC
+0.5
UNIT
°C
°C
V
V
2006 Aug 10
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Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
BLOCK DIAGRAM
CHANNEL
MODE AND
TIMING A/B
DPLL CLK
MUX A/B
D0–D7
BUS
BUFFER
DPLLA/B
BRG
INTERFACE/
OPERATION
CONTROL
A7 CONTROL
LOGIC
A7
ADDRESS
DECODE
COUNTER
TIMER A/B
C/T CLK
MUX A/B
CTCRA/B
RDYN
WRN
RDN
A1–A6
CEN
RESETN
MPU
INTERFACE
R/W
DECODE
DMA
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
RTxDRQAN/GPO1AN
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
EOPN
CONTROL
DMA
INTERFACE
GSR
CMR1A/B
CMR2A/B
OMRA/B
TRCR A/B
FTLR A/B
TRMR A/B
CID
INTERNAL BUS
CTPRHA/B
CTPRLA/B
CTHA/B
CTLA/B
TRANSMIT
A/B
TRANS CLK
MUX
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
16 DEEP
FIFO
TELR
A/B
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
TxD A/B
TRxCA/B
RTxCA/B
CTSAN/LCAN
CTSBN/LCBN
DCDBN/SYNIBN
DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
SPECIAL
FUNCTION
PINS
RECEIVER
A/B
RCVR CLK
MUX
RPRA/B
RTRA/B
S1RA/B
S2RA/B
INTERRUPT
CONTROL
ICRA/B
RCVR
SHIFT REG
RECEIVER
16 DEEP
FIFO
RFLR
A/B
CDUSCC
LOGIC
CRC
ACCUM
BISYNC
COMPARE
LOGIC
RxD A/B
IRQN
IACKN
IERA/B
IVRM
IER1 A/B
IER2 A/B
IER3 A/B
X1/CLK
X2
OSCILLATOR
SD00239
Figure 1. Block diagram
2006 Aug 10
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Philips Semiconductors
Product data sheet
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
PIN CONFIGURATION
INDEX
CORNER
8
7
1
47
46
PLCC
20
21
TOP VIEW
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
IACKN
A3
A2
A1
RTxDAKBN/GPI1BN
IRQN
NC
RDYN
RTSBN/SYNOUTBN
TRxCB
RTxCB
DCDBN/SYNIBN
NC
RxDB
TxDB
TxDAKBN/GPI2BN
RTxDRQBN/GPO1BN
TxDRQBN/GPO2BN/RTSBN
CTSBN/LCBN
D7
D6
D5
D4
RDN
RESETN
GND
33
34
Pin Function
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
CSN
WRN
EOPN
D3
D2
D1
D0
NC
CTSAN/LCAN
TxDRQAN/GPO2AN/RTSAN
RTxDRQAN/GPO1AN
TxDAKAN/GPI2AN
TxDA
RxDA
NC
DCDAN/SYNIAN
RTxCA
TRxCA
RTSAN/SYNOUTAN
X2
X1/CLK
RTxDAKAN/GPI1AN
A6
A5
A4
V
CC
SD00740
Figure 2. Pin configuration
PIN DESCRIPTION
MNEMONIC
A1–A6
D0–D7
PIN
4-2,
51-49
33-30,
23-20
TYPE
I
I/O
NAME AND FUNCTION
Address Lines:
Active-HIGH. Address inputs which specify which of the internal registers is
accessed for read/write operation.
Bidirectional Data Bus:
Active-HIGH, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data,
command and status transfers between the CPU and the CDUSCC take place over this bus. The
data bus is enabled when CSN and RDN, or CSN and WRRN are LOW during interrupt
acknowledge cycles and single address DMA acknowledge cycles.
Read Strobe:
Active-LOW input. When active and CSN is also active, causes the content of the
addressed register to be present on the data bus. RDN is ignored unless CSN is active.
Write Strobe:
Active-LOW input. When active and CSN is also active, the content of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of WRN. WRN is ignored
unless CEN is active.
Chip Select:
Active-LOW input. When active, data transfers between the CPU and the CDUSCC are
enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When CSN is HIGH, the data
lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single
address DMA transfers).
Ready:
Active-LOW, open drain. Used to synchronize data transfers between the CPU and the
CDUSCC. It is valid only during read and write cycles where the CDUSCC is configured in ‘wait on
Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always inactive. RDYN becomes active
on the leading edge of RDN and WRN if the requested operation cannot be performed (viz, no data
in RxFIFO in the case of a read or no room in the TxFIFO in the case of a write).
RDN
WRN
24
28
I
I
CSN
27
I
RDYN
8
O
2006 Aug 10
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