Low Input, MHz Operation,
High Efficiency Synchronous Buck
POWER MANAGEMENT
Description
The SC4609 is a voltage mode step down (buck) regula-
tor controller that provides accurate high efficiency power
conversion from an input supply range of 2.7V to 5.5V. A
high level of integration reduces external component
count, and makes it suitable for low voltage applications
where cost, size and efficiency are critical. The SC4609
is capable of producing an output voltage as low as 0.5V.
It’s frequency of operation is programmable to 1MHz.
The SC4609 drives external, N-channel MOSFETs with a
peak gate current of 1A. A non-overlap protection is pro-
vided for the gate drive signals to prevent shoot through
of the MOSFET pair. The SC4609 features lossless cur-
rent sensing of the voltage drop across the drain to
source resistance of the high side MOSFET during its
conduction period.
The quiescent supply current in sleep mode is typically
lower than 10
µ
A. A external soft start is provided to pre-
vent output voltage overshoot during start-up.
The SC4609 is an ideal choice for converting 3.3V, 5V or
other low input supply voltages. It’s available in 12 pin
MLP package.
SC4609
Features
Asynchronous start up
Operation to 1MHz
BiCMOS voltage mode PWM controller
2.7V to 5.5V input voltage range
Output voltages as low as 0.5V
+/-1% reference accuracy
Sleep mode (Icc = 10µA typ)
Adjustable lossless short circuit current limiting
Combination pulse by pulse & hiccup mode
current limit
High efficiency synchronous switching
1A peak current driver
External soft start
12-pin MLP package
Applications
Distributed power architecture
Servers/workstations
Local microprocessor core power supplies
DSP and I/O power supplies
Battery-powered applications
Telecommunications equipment
Data processing applications
Typical Application Circuit
Vin=2.7V - 5.5V
C10
D2
220u
1u
C17
M11
C13
22u
C14
22u
R3
R13
1
U1
12
C3
4.7u
1
2
3
BST
VCC
ISET
COMP
FSET
VSENSE
DRVH
PHASE
DRVL
PGND
AGND
SS
11
10
9
8
7
6
Css
22u
R6
1
R5
1
M2
330u
L1
1.8u
C9
C6
C5
22u
C4
22u
R8
200
4.7n
R7
10k
Vout=1.5V (as low as 0.5V*) / 12A
C2
C1
180p
2.2n
C16
560pF
4
5
R1
14.3k
SC4609
*External components can be modified to provide a Vout as low as 0.5V
R9
4.99k
Revision: August 24, 2004
1
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SC4609
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Supply Voltage (V
CC
)
PGND
Output Drivers (DRVH, DRVL) Currents
Continuous
P eak
Inputs (VSENSE, COMP, FSET, ISET, SS)
BST
PHASE
PHASE Pulse tpulse < 50ns
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
Peak IR Reflow Temperature, 10 - 40s
ESD Rating (Human Body Model)
Symbol
Maximum
6
±0.3
±0.25
±1.00
-0.3 to 6
12
-0.3 to 6
-2 to 7
Units
V
V
A
A
V
V
V
V
°C
°C
°C
°C
kV
T
A
T
STG
T
J
T
PKG
ESD
-40 to +85
-65 to +150
-55 to +150
260
4
All voltages with respect to AGND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, VCC = 3.3V, CT = 270pF, T
A
= -40°C to 85°C, T
A
=T
J
Note: (1). Guaranteed by design.
Parameter
Overall
Supply Voltage
Supply Current, Sleep
Supply Current, Operating
VCC Turn-on Threshold
VCC Turn-off Hysteresis
Error Amplifier
Input Voltage
(Internal Reference)
Test Conditions
Min
Typ
Max
Unit
5.5
F S E T = 0V
V
CC
= 5.5V
Temperature
350
10
2
15
3.75
2.7
V
µA
mA
V
mV
T
A
= 25°C
V
CC
= 2.7V - 5.5V, T
A
= 25°C
T
A
= -40°C to 85°C
0.495
0.4925
0.4925
0.5
0.5
0.505
V
0.5075
0.5075
VSENSE Bias Current
Open Loop Gain
(1)
Unity Gain Bandwidth
(1)
2004 Semtech Corp.
V
SENSE
= 0.5V
V
COMP
= 0.5 to 2.5V
200
90
8
2
nA
dB
MHz
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SC4609
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, CT = 270pF, T
A
= -40°C to 85°C, T
A
=T
J
Parameter
Error Amplifier (Cont.)
Slew Rate
(1)
VOUT High
VOUT Low
Oscillator
Initial Accuracy
Voltage Stability
Temperature Coefficient
Minimum Operation Frequency
(1)
Maximum Operation Frequency
(1)
Ramp Peak to Valley
Ramp Peak Voltage
Ramp Valley Voltage
Sleep, Soft Start, Current Limit
Sleep Threshold
Sleep Input Bias Current
Programmable Soft Start Time
Soft Start Charge Current
ISET Bias Current
Temperature Coefficient of ISET
Current Limit Blank Time
Gate Drive
DRVH Minimum OFF Time
Peak Source (DRVH)
Peak Sink (DRVH)
Peak Source (DRVL)
Peak Sink (DRVL)
Output Rise Time
Output Fall Time
Minimum Non-Overlap
(1)
2004 Semtech Corp.
(1)
(1)
(1)
Test Conditions
Min
Typ
Max
Unit
2.4
I
COMP
= -5.5mA
I
COMP
= 5.5mA
V
CC
- 0.5
V
CC
- 0.3
0.3
0.45
V/µs
V
T
A
= 25°C
T
A
= 25°C, V
CC
= 2.7V to 5.5V
Temperature
525
575
0.05
0.02
625
kHz
%/V
%/°C
kHz
50
1M
1
1.3
0.3
Hz
V
V
V
Measured at FSET
V
SYNC
= 0V
C = 20nF
T
A
= 25°C
T
J
= 25°C
-45
-1
1.75
-5.75
-50
0.28
130
75
mV
µA
ms
µA
-55
µA
%/°C
ns
T
A
= 25°C, V
SENSE
= 0
Vgs = 3.3V, I
SOURCE
= 100mA
Vgs = 3.3V, I
SINK
= 100mA
Vgs = 3.3V, I
SOURCE
= 100mA
Vgs = 3.3V, I
SINK
= 100mA
Vgs = 3.3V, C
OUT
= 4.7nF
Vgs = 3.3V, C
OUT
= 4.7nF
160
2.7
1.8
2.2
1.5
35
27
40
200
ns
Ω
Ω
Ω
Ω
ns
ns
ns
3
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SC4609
POWER MANAGEMENT
Pin Configuration
TOP VIEW
BST
DRVH PHASE
Ordering Information
Part Number
(1)
SC4609IMLTRT
(2)
Device
MLP-12
12
VCC
1
11
10
9
DRVL
ISET
2
8
PGND
Notes:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead free product.
COMP
3
4
5
6
7
AGND
FSET
VSENSE
SS
(MLP12, 4x4)
Pin Descriptions
Pin #
1
2
Pin Name
VC C
ISET
Pin Function
Positive supply rail for the IC. Bypass this pin to GND with a 0.1 to 4.7µF low ESL/ESR
ceramic capacitor.
The ISET pin is used to limit current in the high side MOSFET. The SC4609 uses the
voltage across the V
IN
and ISET pins in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the V
IN
and PHASE pin.
This is the output of the voltage error amplifier. The voltage at this output is inverted
internally and connected to the non-inverting input of the PWM comparator. A lead-lag
network from the COMP pin to the VSENSE pin compensates for the two pole LC filter
characteristics inherent to voltage mode control. The lead-lag network is required in order
to optimize the dynamic performance of the voltage mode control loop.
The FSET pin is used to sets the PWM oscillator frequency through an external timing
capacitor that is connected from the FSET pin to the GND pin. When the FSET is pulled
and held below 75mV, its sleep mode operation is invoked. Sleep mode operation is
invoked by clamping the FSET pin to a voltage below 75mV. The typical supply current
during sleep mode is 10µA. The SC4609 can be operated in synchronous mode by placing
a resistor in series between the timing capacitor and ground. The other terminal of the
timing capacitor will remain connected to the FSET pin.
This pin is the inverting input of the voltage amplifier and serves as the output voltage
feedback point for the Buck converter. VSENSE is compared to an internal reference value
of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired.
For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical
Application Circuit Diagram).
Soft start. A capacitor to ground sets the soft start time. The soft start time is independent
of switching frequency and is defined as
SS
=
87.5
•
10
3
•
C.
Where C is the external
capacitor in nF and soft start time in second.
4
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3
COMP
4
FS E T
5
VSENSE
6
SS
2004 Semtech Corp.
SC4609
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin #
7
8
9
Pin Name
AGND
PGND
DRVL
Pin Function
Analog ground.
Power ground.
DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The output drivers
are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to
the output stages. The cross conduction of the external MOSFETs is prevented by
monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time
delay optimized for FET turn-off characteristics.
The PHASE pin is used to limit current in the high side MOSFET. The SC4609 uses the
voltage across the V
IN
and ISET pin in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the V
IN
and PHASE pin.
DRVH drives the gate of the high side (main switch) MOSFET. The output drivers are rated
for 1A peak currents. The PWM circuitry provides complementary drive signals to the
output stages. The cross conduction of the external MOSFETs is prevented by monitoring
the voltage on the driver pins of the MOSFET pair in conjunction with a time delay
optimized for FET turn-off characteristics.
This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to
the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a
sufficient gate-to-source voltage level for driving the gate of the high side MOSFET.
10
PHASE
11
DRVH
12
BST
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