SCG2000 Series
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The Connor-Winfield SCG2000 Series
provides high precision phase lock loop
frequency translation for the
telecommunication applications.
SCG2000 Series is well suited for use in
line cards, service termination cards and
similar functions to provide reliable
reference, phase locked, synchronization
and low phase gain for TDM, PDH, SONET
and SDH network equipment. The
SCG2000 Series provides a jitter filtered,
wander following output signal
synchronized to a superior Stratum or peer
input reference signal.
Data Sheet #:
SG029
Page 1
of
20
Features
•
3.3V High
Precision PLL
•
Tri-State Capability
•
Active Alarms
•
Guaranteed Free
Run ±20ppm
•
1 Sec. Acquisition
Time
Bulletin
Page
Revision
Date
Issued By
SG029
1 of 20
A04
29 JAN 02
MBATTS
Rev:
A04
Date:
01 / 29 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
General Description
The SCG2000 Series provides high precision phase lock loop
frequency translation for the telecommunication applications. The
SCG2000 products generate a CMOS output from an intrinsically
low jitter, voltage controlled crystal oscillator. Most models
provide a jitter attenuated, internal reference that is connected to
a Reference Output pin.
SCG2000 Series is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH, SONET
and SDH network equipment . The SCG2000 Series provides a
low phase gain (<0.2dB), jitter filtered, wander following output
signal synchronized to a superior Stratum or peer input reference
signal.
The SCG2000 Series include the following features: Free
Run, Tri-state and alarm outputs for Loss-of-Reference, (LOR),
Loss-of-Lock, (LOL). During the LOR alarm, the SCG2000
will also enter a Free Run state which will guarantee a 20
ppm accurate output. Additionally the Free Run mode may
be entered manually by asserting a high signal to the Free
Run Enable pin. The outputs may be put into the tri-state
high impedance condition for external testing purposes by
asserting a high signal to the Tri-State Enable pin.
The SCG2000 Series are 3.3 Volt components that
typically draw less than 100 mA. All models have an
acquisition time of approximately 1.0 second and can be
used in applications that require temperature rating of 0° -
70° C. All models have a 33W resistor in series with the
oscillator output. The SCG2000 package dimensions are
.775” x .825” x .35” on a six layer FR4 board with surface
mount pins. Parts are assembled using high temperature
solder to withstand surface mount reflow process.
Functional Block Diagram
Figure 1
Tri-State Enable
(Pin 10)
LOL Alarm Output
(Pin 7)
ALARM
DETECTION
Free Run Enable
(Pin 5)
LOR Alarm Output
(Pin 6)
Reference Input
(Pin 8)
DIVIDER
DPFD
ANALOG
FILTER
FREE RUN
CONTROL
VCXO
Oscillator Output
(Pin 9)
Optional Oscillator Output
(Pin 1)
DIVIDER
Input Freq. Select A
(Pin 14)
Reference Output
(Pin 1)
(Not available on
models with optional
oscillator output)
Input Freq. Select B
(Pin 13)
Model Comparison Table
Table 1
Model
SCG2000
SCG2010
SCG2020
SCG2030
SCG2050
SCG2070
Input
Ref Freq
8-64 kHz
19.44 MHz
19.44 MHz
8-64 kHz
8-64 kHz
19.44 MHz
Max
Duty
Cycle
40/60
40/60
40/60
45/55
40/60
40/60
Reference Output
(Pin #1)
= Input Ref Freq.
8 kHz
19.44 MHz
= Input Ref Freq.
19.44 MHz
51.84 MHz, 77.76 MHz
Oscillator Output
(Pin #9)
1.544 MHz to 125.0 MHz
19.44 MHz
77.76 MHz
1.544 MHz to 125.0 MHz
77.76 MHz
51.84 MHz, 77.76 MHz
Ref Output = Osc Output
Tight Duty Cycle
Notes
Basic Model
*Features which differentiate a model from the base model (SCG2000) are highlighted in boldface color and in the notes column.
Data Sheet #:
SG029
Page 2
of
20
Rev:
A04
Date:
01 / 29 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Pin Description
Table 2
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Connection
Reference Output
TCK
TMS
Ground
Free Run Enable/TDI
GND
Loss of Reference (LOR)
Loss of Lock (LOL)
Reference Input
Oscillator Output
Tri-State enable
Vcc
TDO
Input Freq. Select B
Input Freq. Select A
All SCG2000 Models
Description
Output frequency is dependent on SCG model
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Ground
Free Run enable pin. 1 = Free Run at nominal frequency ±20ppm. Input is pulled to
Alarm indicator. 1 = The reference has been lost.
Alarm indicator. 1 = Phase lock has been lost
Input reference frequency
Output frequency is dependent on SCG model
Tri State control for all outputs. 1 = Hi-Z, 0 = normal. Input is pulled to GND.
3.3V Supply Voltage.
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Control pin B used to select input frequency. Input is pulled to GND.
Control pin A used to select input frequency. Input is pulled to GND.
Typical Application
Figure 2
BITS
System
Signal
Input Select
Line Card 1
A
A
B
M
UX
Y
CW STM/MSTM m
’s
odule
B
S
M
UX
Y
CW SCG
’s
2000/4000
Clock out
S
RCV
Tim Card #N
ing
A
A
B
M
UX
Y
CW STM/M
’s
STM m
odule
M
UX
B
Line Card N
S
CW SCG
’s
2000/4000
Clock out
Y
S
RCV
System Select
Data Sheet #:
SG029
Page 3
of
20
Rev:
A04
Date:
01 / 29 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Absolute Maximum Rating
Table 3
Symbol
Vcc
V1
Ts
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
-0.5
-0.5
-65
All SCG2000 Models
Minimum
Nominal
Maximum
4
5.5
150
Units
Volts
Volts
deg. C
Notes
Specifications
Table 4
Parameter
Voltage
Current
Temperature Range
Input Jitter Tolerance
Jitter Bandwidth
Acquisition Time
Capture/Pull-in Range
Output Duty Cycle
Output Rise and Fall Time
Output Load
Alarms
Free Run Accuracy
Package
TDEV
MTIE
All SCG2000 Models
Specifications
3.3V ±5%
100 mA
0 to 70°C
6.25 us, 10 Hz (.05 UI @ 8000 Hz)
<10 Hz
Approx 1.0 second
±25 ppm Minimum
40/60 % Min/Max @ 50% Level
3 ns @ 20% to 80% output level
30 pF
LOR, LOL Status on seperate outputs
±20 ppm
Fr4 SM 0.775" x .825" x 0.350"
<0.4
ns Typical
2 ns Typical
2.0
Notes
1.0
Input And Output Characteristics
Table 5
Symbol
V
IH
V
IL
T
IO
C
O
V
HO
V
IO
T
IR
Parameter
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
Output Capacitance
High Level Output Voltage l
oH
= -4mA
Low Level Output Voltage l
oL
= 8mA
Input Reference Signal Pulse Width
30
2.4
0.4
nS
All SCG2000 Models
Minimum
2
0
Nominal
Maximum
5.5
0.8
10
10
Units
V
V
nS
pF
Vcc Min.
Vcc Max.
Notes
NOTES:
`
1.0: Requires external regulation
2.0: From a 20 ppm offset in reference frequency
Data Sheet #:
SG029
Page 4
of
20
Rev:
A04
Date:
01 / 29 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Output Jitter Specifications
Table 6
Frequency (MHz)
1.544
2.048
16.384
19.44
20.48
37.056
44.736
49.152
51.84
77.76
125.0
pS (RMS)
TBD
60
35
50
TBD
30
30
30
TBD
30
30
All SCG2000 Models
Jitter BW 10 Hz - 1 MHz
m UI
TBD
0.122
0.573
0.972
TBD
1.11
1.34
1.47
TBD
2.33
3.75
TBD
4
2.25
2.4
TBD
1.25
1.15
1.25
TBD
2.25
1.5
Sonnet Jitter BW 12 KHz - 20 MHz
pS (RMS)
m UI
TBD
0.008
0.037
0.047
TBD
0.046
0.051
0.061
TBD
0.175
0.186
Output Programming
Table 7
Tristate
0
1
0
0
X
1
Alarm Status
Table 8
0
1
X
0
0
1
All SCG2000 Models
Free Run
Output
Locked to reference selected (default)
Hi-Z Tristate condition
Free run at nominal frequency
All SCG2000 Models
Alarm Output
No alarm
Loss-of-Lock
Loss-of-Reference
LOL Output LOR Output
Package Dimensions
Figure 3
Recommended Footprint Dimensions
Figure 4
0.800
0.640
(20.32mm)
(16.26mm)
0.050 TYP
(1.27mm)
0.080 (2.03mm)
0.100 TYP
(2.54mm)
Pin 1
ÃQvÃ8yhh
vÃvÃ#
*Pin Coplanarity is ±0.004”
0.050 TYP
(1.27mm)
0.650
(16.51mm)
Data Sheet #:
SG029
Page 5
of
20
Rev:
A04
Date:
01 / 29 / 02
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
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