MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69C433/D
16K x 64 CAM
The MCM69C433 is a flexible content–addressable memory (CAM) that can
contain 16K entries of 64 bits each. The widths of the match field and the output
field are programmable, and the match time is designed to be 240 ns. As a result,
the MCM69C433 is well suited for datacom applications such as Virtual Path
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C433 is
user–defined, with a trade–off between the time between the match request rate
and the rate of new entries added to the CAM per second.
MCM69C433
SCM69C433
Freescale Semiconductor, Inc...
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•
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16K Entries
240 ns Match Time
Mask Register to “Don’t Care” Selected Bits
O
Depth Expansion by Cascading Multiple Devices
IC
66 MHz Maximum Clock Rate
EM
S
Programmable Match and Output Field Widths
E
Concurrent Matching of Virtual Path Circuits and Virtual Connection
AL
Circuits in ATM Mode
SC
Separate Ports for Control and Match Operations
E
RE
450 ns Insertion Time if 1 of 14 Entry Queue Locations is Empty
F
120 ms Initialization Time After Fast Insertion (at Power–Up Only)
Y
B
Single 3.3 V
±5%
Supply
ED
IEEE Standard 1149.1 Test Port (JTAG)
IV
100–Pin TQFP Package
H
,I
OR
CT
DU
N
C.
N
TQ PACKAGE
TQFP
CASE 983A–01
Related Products
RC
A
— MCM69C232, MCM69C432, MCM69C233 (CAMs)
CONTROL PORT
14 x 64
ENTRY QUEUE
MATCH PORT
MQ31 – MQ0
A2 – A0
DQ15 – DQ0
SEL
WE
IRQ
DTACK
RESET
KMODE
INPUT REG
STATUS/
CONTROL
LOGIC
16K x 64
CAM
TABLE
K
G
LH/SM
LL
MC
MS
VPC
REV 3
6/11/01
©
Motorola, Inc. 2001
MOTOROLA FAST SRAM
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MCM69C433•SCM69C433
1
Freescale Semiconductor, Inc.
PIN ASSIGNMENT
MQ10
MQ11
VSS
VDD
MQ12
MQ13
MQ14
MQ15
LL
VDD
VSS
LH/SM
MQ16
MQ17
MQ18
MQ19
VDD
VSS
MQ20
MQ21
MQ9
MQ8
VSS
VDD
MQ7
MQ6
MQ5
MQ4
VSS
VDD
MQ3
MQ2
MQ1
MQ0
VSS
VDD
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
DQ9
DQ8
VDD
VSS
DQ7
DQ6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Freescale Semiconductor, Inc...
CH
AR
ED
IV
BY
EE
FR
LE
CA
S
S
O
IC
EM
,I
OR
CT
DU
N
MQ22
MQ23
VSS
VDD
MQ24
MQ25
MQ26
MQ27
VSS
VDD
MQ28
MQ29
MQ30
MQ31
VSS
VDD
MC
VPC
MS
G
VSS
VDD
DTACK
IRQ
RESET
TDO
VDD
VSS
TCK
TMS
C.
N
MCM69C433•SCM69C433
2
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DQ5
DQ4
VDD
VSS
DQ3
DQ2
DQ1
DQ0
K
VSS
VDD
A2
A1
A0
WE
SEL
KMODE
VDD
TRST
TDI
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
PIN DESCRIPTIONS
Pin Locations
42 – 44
58
17 – 20, 23 – 26,
29 – 32, 35 – 38
61
57
39
47
89
92
64
Symbol
A2 – A0
DTACK
DQ15 – DQ0
G
IRQ
K
KMODE
LH/SM
LL
MC
MQ31 – MQ0
Type
Input
Output
I/O
Input
Output
Input
Input
Input
3–bit control port address bus.
Control port data transfer acknowledge (Open Drain).
16–bit bidirectional control port data bus.
Output Enable control of MQ31 – MQ0.
Control port interrupt (Open Drain).
Interface Clock, max frequency of 66 MHz.
See Note.
Description
Freescale Semiconductor, Inc...
67 – 70, 73 – 76,
79 – 82, 85 – 88,
93 – 96, 99, 100,
1, 2, 5 – 8, 11 – 14
62
56
46
52
50
55
51
49
63
45
4, 10, 16, 22, 27, 33,
41, 48, 54, 59, 65, 71,
77, 84, 91, 97
3, 9, 15, 21, 28, 34,
40, 53, 60, 66, 72,
78, 83, 90, 98
MS
RESET
SEL
TCK
TDI
CH
TRST
AR
TMS
VPC
WE
VDD
TDO
ED
Output
IV
Input
Input
Output
Input
,I
Input
Latch Low. Latches low order bits if match width is > 32 bits.
OR
CT
Output
Match Complete (Open Drain).
DU
input of match RAM and data RAM
I/O
32–bit common I/O CAM data.
N
for
Used
O
values.
IC
EM
S
E
Output
Match Successful (Open Drain).
AL
to a known state.
Input
Resets chip
SC
Input
Control
EE
port chip select, active low.
R
Test Clock, part of JTAG interface.
Input
F
BY
Input
Test Data In, part of JTAG interface.
Test Data Out, part of JTAG interface.
Test Mode Select, part of JTAG interface.
Tap Reset part of JTAG interface.
Latch High/Start Match. Initiates match sequence on match data present on
MQ31 – MQ0.
C.
N
Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has
occurred (Open Drain).
Control port Write Enable.
Power Supply: 3.3 V
±5%.
Supply
VSS
Supply
Ground.
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
K
RESET
KMODE
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MCM69C433•SCM69C433
3
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Supply Voltage (see Note 2)
Voltage Relative to VSS (see Note 2)
Output Current per Pin
Package Power Dissipation (see Note 3)
Temperature Under Bias (see Note 3)
Commercial
Industrial
Operating Temperature
Storage Temperature
Commercial
Industrial
Symbol
VDD
Vin
Iout
PD
Tbias
–10 to 85
–40 to 85
TA
Tstg
0 to 70
–40 to 85
–55 to 125
°C
°C
Value
4.6
–0.5 to VDD + 3 V
±20
—
Unit
V
V
mA
W
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Freescale Semiconductor, Inc...
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
S
E
AL
DC OPERATING CONDITIONS AND CHARACTERISTICS
C
(VDD = 3.3 V
±5%,
T
S
< 120°C, Unless Otherwise Noted)
J
EE
FR
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Y
Symbol
Min
Parameter
B
D
Power Supply Voltage
VDD
3.1
VE
I
Operating Temperature (Junction)
TJ
—
CH
R
Input Low Voltage
VIL
–0.5*
A
Input High Voltage
O
IC
EM
,I
OR
CT
DU
N
C.
N
Typ
3.3
—
0
3
Max
3.5
120
0.8
5.5
Unit
V
°C
V
V
* VIL (min) = –3.0 V ac (pulse width
v
20 ns).
Parameter
VIH
2.2
DC CHARACTERISTICS AND SUPPLY CURRENTS
Symbol
IDDA
Ilkg(I)
Ilkg(O)
VOL
VOH
Min
—
—
—
—
2.4
Max
300
±1
±1
0.4
—
Unit
mA
µA
µA
V
V
Active Power Supply Current
Input Leakage Current (0 V
v
Vin
v
VDD)
Output Leakage Current (0 V
v
Vin
v
VDD)
Output Low Voltage (IOL = 8 mA)
Output High Voltage (IOH = –4 mA)
PACKAGE THERMAL CHARACTERISTICS
Rating
Thermal Resistance Junction to Ambient (200 lfpm, 4 Layer Board) (see Note 2)
Thermal Resistance Junction to Board (Bottom) (see Note 3)
Thermal Resistance Junction to Case (Top) (see Note 4)
Symbol
R
θJA
R
θJB
R
θJC
Max
36
19
8
Unit
°C/W
°C/W
°C/W
NOTES:
1. RAM junction temperature is a function of on–chip power dissipation, package thermal impedance, mounting site temperature, and
mounting site thermal impedance.
2. Per SEMI G38–87.
3. Indicates the average thermal impedance between the die and the mounting surface.
4. Indicates the average thermal impedance between the die and the case top surface. Measured via the cold plate method (MIL SPEC–883
Method 1012.1).
MCM69C433•SCM69C433
4
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
CAPACITANCE
(Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
I/O Capacitance
Symbol
Cin
CI/O
Min
—
—
Max
5
8
Unit
pF
pF
JUNCTION TO AMBIENT THERMAL CHARACTERISTICS
Board
1 Layer
1 Layer
4 Layer
4 Layer
Air (LFPM)
0
200
0
200
θ
JA (°C/W)
43
36
33
29
Freescale Semiconductor, Inc...
,I
OR
AC OPERATING CONDITIONS AND CHARACTERISTICS
CT
(VDD = 3.3 V
±5%,
TJ < 120°C, Unless Otherwise
U
D
Noted)
N
O
Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing
IC
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
EM
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
S
E
CONTROL PORT TIMINGS
AL
(Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent and Listed Values are for tKHKH = 15 ns)
SC
EE
Parameter
Symbol
Min
Max
Unit
Notes
FR
Address Valid to SEL Low
tAVSL
0
—
ns
BY
DTACK Low to Address Invalid
tDTLAX
0
—
ns
ED
V
Data Valid to Select Low
tDVSL
0
—
ns
HI
C
DTACK Low to Data Invalid
tDTLDX
0
—
ns
AR
Output Valid to DTACK Low
WE Valid to Select Low
DTACK Low to WE High
WE High to Output Active
Select Low to DTACK Low
Select High to DTACK High
DTACK Low to IRQ Low
IRQ Low to IRQ High
DTACK Low to Select High
DTACK High to Select Low
Address Valid to Output Valid
Select High to Output High Impedance
RESET Low to RESET High
tQVDTL
tWVSL
tDTLWH
tWHQX
tSLDTL
tSHDTH
tDTLIL
tILIH
tDTLSH
tDTHSL
tAVQV
tSHQZ
tRLRH
2
0
0
2
10
10
10
20
0
0
—
—
2 x tKHKH
—
—
—
—
—
—
—
—
—
—
8
8
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
C.
N
NOTE:
1. DTACK is delayed when a write is attempted during certain operations. See Functional Description.
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MCM69C433•SCM69C433
5
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