SD-14550 Series Data Sheet
Make sure the next
Card you purchase
has...
®
PROGRAMMABLE SYNCHRO/
RESOLVER-TO-DIGITAL CONVERTERS
FEATURES
•
Synthesized Reference Option
•
1 Minute Accuracy Available
(“S” Option only)
•
Single +5 V Power Supply
•
10-, 12-, 14-, or 16-Bit Programmable
Resolution
•
Small 34-Pin Ceramic Package
•
BIT Output
•
Velocity Output Eliminates
Tachometer
•
High Reliability Single Chip
Monolithic
DESCRIPTION
The SD-14550 Series are small complete low cost hybrid Synchro- or
Resolver-to-Digital converters based on a single-chip monolithic. The
SD-14550X “S” option offers synthesized reference circuitry to correct
for phase shifts between the reference and signal voltage. The com-
pletely self-contained unit offers programmable resolution and +5
VDC operation. The package is a 34-pin, 1.0 x 0.78 x 0.21 inch
ceramic package.
Resolution programming allows selection of 10-, 12-, 14-, or 16-bit
modes. This feature allows selection of either low resolution for fast
tracking or higher resolution for higher accuracy.
The velocity output (VEL) from the SD-14550, which can be used to
replace a tachometer, is a ±4 V signal referenced to analog ground
with a linearity of 1% of output voltage.
This converter series also offers a Built-In-Test output (BIT). The SD-
14550 converters are available with operating temperature ranges of
0°C to +70°C, -40°C to +85°C and -55°C to +125°C. These convert-
ers are also available with MIL-PRF-38534 processing.
•
-55°C to +125°C Operating
Temperature Range
•
MIL-PRF-38534 Processing Available
APPLICATIONS
With its low cost, small size, high accuracy, and versatile perform-
ance, the SD-14550 Series converters are ideal for use in modern
high-performance military, commercial and space position control
systems. Typical applications include radar antenna positioning, nav-
igation and fire control systems, motor control, and robotics.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1991, 1999 Data Device Corporation
RH
BIT
R
BIT
DETECTOR
C
I
LOS
ERROR
R
I
GAIN
B
A
HYSTERESIS
INTEGRATOR
DEMODULATOR
"S" OPTION
SYNTHESIZED REFERENCE
REFERENCE CONDITIONER
Data Device Corporation
www.ddc-web.com
RL
S1
INPUT OPTION
CONTROL
TRANSFORMER
VEL
S2
S3
S4
2
+5 V
+5 V
14/16 BIT
UP/DOWN
COUNTER
VCO & TIMING
DC-DC
CONVERTER
-5 V
FILTER
33 µf
external
capacitor
DATA LATCHES
8
8
EM DATA
EL
INH
A
B
SD-14550 Series
M-03/12-0
FIGURE 1. SD-14550 SERIES BLOCK DIAGRAM
TABLE 1. SD-14550 SERIES SPECIFICATIONS
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; 10% signal amplitude variation, and 10% har-
monic distortion.
PARAMETER
UNIT
VALUE
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
SD-14550
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
SD-14550XS
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
±Sig/Ref Phase Shift
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
2 V Direct Input (L-L)
Voltage Range
Max. Voltage w/o Damage
Input Impedance
2 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
DIGITAL INPUT/OUTPUT
LOGIC TYPE
INPUTS
Bits
Min
LSB
LSB
programmable 10, 12, 14, or 16
1, 2 or 4, + 1 LSB (see TABLE 4)
1 max.
1 max.
(RH, RL)
differential
2 & 11.8 V UNITS
90 V UNIT
2-35
10-130
360 - 5K
60 (47-5K)
400 (360-5K)
60K
120K
50,
100 transient
2-35
1K - 5K
270K min.
540K min.
200,
300 transient
—
—
TABLE 1. SD-14550 SERIES SPECS (CONT)
PARAMETER
DIGITAL INPUT/OUTPUT
INPUTS
(CONTINUED)
Inhibit (lNH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Logic 0 inhibits; Data
stable within 0.5 µs
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
UNIT
VALUE
Vrms
Hz
OUTPUTS
Parallel Data (see Note 2)
Built-In-Test
Ohm
Ohm
Vpeak
Vrms
Hz
Drive Capability
Ohm
Ohm
Vpeak
deg.
40K
80K
50,
100 transient
45 max.
—
—
—
—
16 parallel lines; 2 bytes
natural binary angle, posi-
tive logic.
LOGIC 0 = BIT condition.
~ 100 LSBs of positive
error, ~ 250 LSB’s of nega-
tive error, with a filter of 500
µs for LOS.
(LOS and LOR for “S” option)
50 PF +
TTL
Logic 0; 1 TTL load, 1.6 mA
at 0.4 V max
Logic 1; 10 TTL loads,
-0.4 mA at 2.8 V min
CMOS Logic 0; 100mV max. driving
Logic 1; +5 V supply minus
100 mV min.
bits
Ohm
Ohm
V
123K
80K
180 max.
Ohm
Ohm
V
52K
34K
30 max.
(same for “S” option)
140K
70K
30 max.
VELOCITY CHARACTERISTICS
(see Note 1.)
Polarity
Positive for increasing angle
Voltage Range (Full Scale)
±V
4.0 typ.
3.5 min.
(see Note 2)
Scale Factor
±%
10 typ.
20 max.
Scale Factor TC
ppm/°C 100 typ.
200 max.
Reversal Error
±%
1 typ.
2 max.
Linearity
±%
0.5 typ.
1 max.
Zero Offset
mV
5 typ.
10 max.
Zero Offset TC
µV/°C
15 typ.
30 max.
Load
KOhm
20 min.
Noise
(Vp/V)%
1 typ.
2 max.
POWER SUPPLIES
Nominal Voltage
Voltage Tolerance
Max. Voltage w/o Damage
Current
“S” option
TEMPERATURE RANGE
Operating
-30X
-20X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
V
%
V
mA
mA
+5
±5
+7
30 typ.
30 typ.
Ohm
Ohm
V
35 max.
35 max.
Vrms
V
Ohm
2 nom, 2.3 max.
25 cont, 100 pk transient
20 M || 10 pF min.
(“S” option only)
11K
22K
4.9 max.
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max P current
.U.
source to +5 V || 5 pF max.
CMOS transient protected.
See TABLE 2.
Ohm
Ohm
V
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-65 to +150
in
(mm)
oz
(g)
1.00 x 0.78 x 0.21
(25.4 x 19.81 x 5.33)
0.44
(12.47)
Resolution Control
NOTES:
1. Refer to TABLE 3 for full-scale tracking rate.
2. Dynamic accuracy may be degraded in high bandwidth sys-
tem applications. See Theory of Operation section for details.
Data Device Corporation
www.ddc-web.com
3
SD-14550 Series
M-03/12-0
THEORY OF OPERATION
The SD-14550 Series of converters are based upon a single chip
CMOS custom monolithic. They are implemented using the latest
IC technology, which merges precision analog circuitry with digi-
tal logic to form a complete high performance tracking
Synchro/Resolver-to-Digital converter.
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
using the SD-14550 Series converters:
1) The power supply is +5 V DC.
2) Direct inputs are referenced to AGND.
CONVERTER OPERATION
Figure 1 is the functional block diagram of the SD-14550 Series.
The converter operates with a single +5 V DC power supply and
internally generates a negative voltage of approximately 5 volts.
This negative voltage comes out on pin 5 (filter point) — see
GENERAL SETUP CONSIDERATIONS.
The converter is made up of three main sections; an input front-
end, an error processor, and a digital interface. The converter
front-end differs for synchro, resolver and direct inputs. An elec-
tronic Scott-T is used for synchro inputs, a resolver conditioner
for resolver inputs, and a sine and cosine voltage follower for
direct inputs. These amplifiers feed the high accuracy Control
Transformer (CT). Its other input is the 16-bit digital angle
φ.
Its
output is an analog error angle, or difference angle, between the
two inputs. The CT performs the ratiometric trigonometric com-
putation of SINθCOSφ - COSθSINφ = SIN(θ -
φ)
using amplifiers,
switches, logic, and capacitors in precision ratios.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters ratioed capacitors
are used in the CT, instead of the more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate to eliminate this
drifting and at the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which in turn drives a volt-
age controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant voltage input to position rate output) which
together with the velocity integrator forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop and another lag at higher frequency is introduced
to reduce the gain and ripple at the carrier frequency and above.
Dynamic accuracy may be degraded in applications with a high
system bandwidth. This dynamic accuracy error is usually not an
issue when using the device’s analog velocity output or position
output data in a control-loop because they are inherently filtered
due to comparatively low bandwidths in most applications.
3) Connect (close to hybrid) pin 31 (Analog Ground) to pin 7
(GND).
4) Connect a 33 µF/10 VDC tantalum filter capacitor externally
between pin 5 (filter point) to pin 7 (ground).
PROGRAMMABLE RESOLUTION
Resolution is controlled by pins 27 and 28. The resolution can be
changed during converter operation so that the appropriate res-
olution and velocity dynamics can be set as needed. To insure
that a race condition does not exist between counting and chang-
ing the resolution, the resolution control is latched internally.
Refer to TABLE 2 for resolution control.
TABLE 2. RESOLUTION CONTROL (A AND B)
RESOLUTION
10 BIT
12 BIT
14 BIT
16 BIT
B
0
0
1
1
A
0
1
0
1
BIT (BUILT-IN-TEST)
This output is a logic line that will flag an internal fault condition
or LOS (Loss-Of-Signal). The internal fault detector monitors the
internal loop error and, when it exceeds approximately 100 LSBs
of positive or 250 LSBs of negative error, will set the line to a
logic 0; this condition will occur during a large-step input and will
reset to a logic 1 after the converter settles out. (The error volt-
age is filtered with a 500 µs filter.) BIT will set for an over veloci-
ty condition because the converter loop cannot maintain
input/output sync. BIT will also be set if a total LOS (loss of all
signals) occurs. Additionally, in the SD-14550XS version, BIT will
set when a Loss-of-Reference (LOR) condition occurs.
Data Device Corporation
www.ddc-web.com
4
SD-14550 Series
M-03/12-0
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a con-
verter without the “false 180° hangup” feature may fail to
respond.
The condition is artificial, as a “real” synchro or resolver cannot
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
INTERFACING
SOLID-STATE BUFFER PROTECTION - TRANSIENT
VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The recurrent AC peak
+ DC common mode voltage should not exceed the values in
TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 300 V specification listed in TABLE 1.
These tran-
sients can destroy the thin-film input resistor network in the
hybrid.
Therefore, 90 V L-L solid-state input modules may be
protected by installing voltage suppressors as shown in FIGURE
2. Voltage transients are likely to occur whenever a synchro is
switched on and off. For instance, a 1000 V transient can be gen-
erated when the primary of a CX or TX input is opened.
SYNTHESIZED REFERENCE
The synthesized reference section (“S” option) eliminates errors
due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. Due to the inductive nature of synchros and
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature volt-
ages are not completely eliminated. As shown in FIGURE 1, the
converter synthesizes its own internal reference signal based on
the SIN and COS signal inputs. Therefore, the phase of the syn-
thesized (internal) reference is determined by the signal input,
resulting in reduced quadrature errors. The synthesized refer-
ence circuit also eliminates the 180 degree false error null hang
up.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while the data is being trans-
ferred. Application of an inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in 2
bytes. This Enable MSB (EM) is used for the most significant 8
bits and Enable LSB (EL) is used for the least significant bits. As
FOR 90 V SYNCHRO INPUTS
S3
CR1
S1
CR2
S2
RL
S1
90 V
SYNCHRO
INPUT
CR1, CR2, AND CR3 ARE IN6068A, BIPOLAR TRANSIENT
VOLTAGE SUPRESSORS OR EQUIVALENT.
115 V
REF.
INPUT
CR3
S2
S3
RH
HYBRID
1N6071A
FIGURE 2. CONNECTIONS FOR VOLTAGE TRANSIENT SUPPRESSORS
INHIBIT
500 ns max
EM OR EL
150 ns MAX
100 ns MAX
DATA
DATA
VALID
DATA
HIGH Z
DATA
VALID
HIGH Z
FIGURE 3. INHIBIT TIMING
Data Device Corporation
www.ddc-web.com
5
FIGURE 4. ENABLE TIMING
SD-14550 Series
M-03/12-0
