SD-14590/91/92
SYNCHRO-TO-DIGITAL CONVERTERS
DESCRIPTION
The SD-14590/91/92 series are high
reliability synchro- or resolver-to-dig-
ital converters with 14-bit-only, 16-
bit-only, or 14- or 16-bit programma-
ble resolution. This series of convert-
ers feature high quality velocity out-
put and hermetically sealed pack-
ages. In addition, the SD-14591 and
SD-14592 are pin-for-pin replace-
ments for the Natel 1024 and 1026,
respectively.
User-programmable resolution has
been designed into the SD-14590 to
increase the capabilities of modern
motion control systems. The precise
positioning attained at 16 bits of reso-
lution and fast tracking of a 14-bit
device are now available from one 36-
pin double DIP hybrid. Velocity output
(VEL) from the SD-14590/91/92 is a
V-based voltage of 0 to ±3.5 VDC with
a linearity to 2.0%. Output voltage is
positive for an increasing angle.
The digital angle output from the SD-
14590/91/92 is a natural binary code,
parallel positive logic and is TTL/CMOS
compatible. Synchronization to a com-
puter is accomplished via a converter
busy (CB) and an inhibit (INH) input.
FEATURES
•
•
•
•
•
•
•
Replacement for NATEL’S 1024
and 1026
High Quality Velocity Output
Eliminates Tachometer
Accuracy to ±1.3 Arc Minutes
Small Size
Synchro or Resolver Input
Synthesized Reference
Eliminates 180° Lock-Up
APPLICATIONS
Because of its high reliability, accuracy,
small size, and low power consumption,
the SD-14590/91/92 is ideal for the
most stringent and severe industrial and
military ground or avionics applications.
All models are available with MIL-PRF-
38534 processing as a standard option.
Designed with three-state output, the
SD-14590/91/92 is especially well-
suited for use with computer based
systems. Among the many possible
applications are radar and navigation
systems, fire control systems, flight
instrumentation, and flight trainers or
simulators.
SOLID STATE SYNCHRO INPUT OPTION
SOLID STATE RESOLVER INPUT OPTION
DIRECT INPUT OPTION
SIN
θ
COS
θ
VOLTAGE
FOLLOWER
BUFFER
SIN
θ
COS
θ
INTERNAL
DC
REFERENCE
REF IN
RH
RL
GND
+15 V
BIT
S1
S2
S3
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
S4
RESOLVER
CONDITIONER
SIN
θ
COS
θ
INPUT OPTIONS
V
REFERENCE
CONDITIONER
R
SYNTHESIZED
REF
BIT DETECT
UNITY
GAIN
BUFFER
e
UNITY
GAIN
BUFFER
VEL
SIN
θ
INPUT OPTION
COS
θ
HIGH ACCURACY
CONTROL
TRANSFORMER
GAIN
e
SIN
(θ-φ)
DEMOD
D
ERROR
PROCESSOR
VEL
T
VCO
U
E
1 LSB ANTIJITTER FEEDBACK
16 BIT CT
TRANSPARENT
LATCH
U
50 ns DELAY
T
INH
EDGE
T
TRIGGERED
LATCH
A
RESOLUTION CONTROL (14590 ONLY)
0.4-1 µs
CB
+5 V
DIGITAL
ANGLE
φ
16 BIT U-D
COUNTER
Q
INHIBIT
TRANSPARENT
LATCH
POWER
SUPPLY
CONDITIONER
INH
3 STATE
TTL BUFFER
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
+10 V
INTERNAL DC
REF V (+5 V)
+15V
EM
BITS 1-8
BITS 9-14/16
EL
FIGURE 1. SD-14590/91/92 BLOCK DIAGRAM
©
1996, 1999 Data Device Corporation
TABLE 1. SD-14590/91/92 SPECIFICATIONS
Apply over temperature range, power supply range, reference, fre-
quency and amplitude ranges; 10% signal amplitude variation; and up
to 10% harmonic distortion in the reference.
PARAMETER
RESOLUTION
(1)
ACCURACY
(2)
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Ranges
Nominal 400 Hz Units
Nominal 60 Hz Units
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance balanced)
Synchro
Zin Line to Line
Zin Each Line to Gnd
Resolver
Zin Single Ended
Zin Differential
Zin Each Line to Gnd
Common Mode Range
Direct ( 1 V
L-L
)
Input Signal Type
UNIT
Bits
Min
LSB
LSB
VALUE
14, 16, 14 / 16
±4, ±2, or ±1 +1 LSB
1 max
1 max in the 16th bit
TABLE 1. SD-14590/91/92 SPECIFICATIONS
(contd)
PARAMETER
Output Parallel Data
UNIT
bits
VALUE
14 or 16 parallel lines; nat-
ural binary angle, positive
logic
0.4 to 2 µs positive pulse;
leading edge initiates
counter update.
Logic 1 for fault.
50 pF plus rated logic drive.
Logic 0; 1 TTL load,
1.6 mA at 0.4 Vmax
Logic 1; 10 TTL loads
0.4 mA at 2.8 V min
High Z; 10 µA//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply minus
100 mV min driving CMOS
Converter Busy (CB)
BIT
Drive Capability
Hz
Hz
Vrms
Ohm
Ohm
V
360-1000
47-1000
4-130
250k min
500k min
210 peak max
500 transient peak
ANALOG OUTPUTS
Velocity (VEL)
AC error (e)
See TABLES 3 and 4
mV rms 3.125 16 bit mode
6.130 14 bit mode
V
Ohm
Ohm
V
Ohm
Ohm
Ohm
V
11.8 V
L-L
17.5k
11.5k
11.8 V
L-L
23k
46k
23k
25 max
90 V
L-L
130k
85k
26 V
L-L
50k
100k
50k
60 max
Bias Voltage (V)
Load
DYNAMIC
CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Range
Max Voltage w/o Damage
Current
TEMPERATURE RANGES
Operating
-30X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
kOhm
1/3 Vs ±10%
3 min
See TABLE 3.
Sin/Cos Voltage Range
Max Voltage w/o Damage
Input Impedance
REFERENCE SYNTHESIZER
±Sig/Ref Phase Shift
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Vrms
Ohm
Sin and Cos resolver signals
referenced to converter inter-
nal DC reference V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M//10 pF
voltage follower
45 typ, 60 max
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 µA max P.U.
current source
to +5 V//5 pF max
CMOS transient protected
Logic 0 inhibits
Data stable after 0.5 µs
Logic 0 enables
Logic 1 High Z
30µA
Logic 0 enables
Logic 1 High Z
30µA
1
0
14 bits
16 bits
+15 V
±%
5
+18
V
mA max 25
+5 V
10
+8
10
Deg
°C
°C
°C
0 to +70
-55 to +125
-65 to +150
Weight
TRANSFORMERS
CHARACTERISTICS
(See ordering information for
list of Transformers. Reference
Transformers are Optional for
Both Solid-State and Voltage
Follower Input Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
in. (mm) 1.9 x 0.78 x 0.21
(48.3 x 19.8 x 5.3)
36 Pin Double Dip
oz
0.7 max (20 g)
Inhibit (INH)
Enable MSB’s (EM)
(3)
Pull down
Enable LSB’s (EL)
(3)
Pull down
Resolution Control (A )
(SD-14590 only)
(Unused Output Data
Bits Are Set to 0)
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
2
TABLE1. SD-14590/91/92 SPECIFICATIONS
(contd)
PARAMETER
TRANSFORMERS
CHARACTERISTICS
(Cont’d)
Signal Transformer
Carrier Frequency Range
Breakdown Voltage to GND
Minimum Input Impedances
(Balanced)
90 V
L-L
26 V
L-L
11.8 V
L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
UNIT
VALUE
360-1000 Hz
700 V peak
Synchro Z
IN
(Z
SO
) Resolver Z
lN
180
Ω
-
20k
Ω
100k
Ω
30k
Ω
30k
Ω
input terminals. Synchro signals, which are of the form sinθ
cosωt, sin(θ + 120°)cosωt, and sin(θ + 240°)cosωt are internally
converted to resolver format; sinθcosωt and cosθcosωt. Direct
inputs accept 1 Vrms inputs in resolver form, (sinθcosωt and
cosθcosωt) and are buffered prior to conversion. FIGURE 2 illus-
trates synchro and resolver signals as a function of the angle
θ.
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection.
Input
impedance is maintained with power off.
SOLID-STATE BUFFER INPUT PRODUCTION:
TRANSIENT VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The current AC peak
+DC common mode voltage should not exceed the values in
TABLE 1.
90 V line-to-line systems may have voltage transients which
exceed the 500 V specification. These transients can destroy the
thin-film input resistor network in the hybrid. Therefore, 90 V
L
-
L
solid-state input modules may be protected by installing voltage
suppressors as shown. Voltage transients are likely to occur
whenever synchro or resolver are switched on and off. For
instance, a 1000 V transient can be generated when the prima-
ry of a CX or TX driving a synchro or resolver input is opened.
See FIGURE 3.
Output Voltage
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
47 - 440 Hz
80 - 138 V rms; 115 V rms
nominal resistive
600 kΩ min resistive
500 V rms transformer
isolated
+R (in phase with RH-RL)
and - R (in phase with RL- RH)
derived from op-amps. Short-
Circuit proof.
3.0 V nominal riding on ground
reference V. Output Voltage
level tracks input level.
4 mA typ, 7 mA max from
+15 V supply.
47 - 440 Hz
10 - 100 V rms L-L; 90 V rms
L-L nominal
148 kΩ min L-L balanced
resistive
±500 V rms transformer isolated
Resolver output:
- sine (- S) + cosine (+C)
derived from op-amps.
Short-circuit proof.
1.0 V rms nominal riding on
ground reference V.
Output voltage level tracks
input level.
4 mA typ, 7 mA max from
+15 V supply.
FEEDBACK LOOP
The feedback loop produces a digital angle
φ
which tracks the
analog input angle
θ
to within the specified accuracy of the con-
+V
S1-S3 = V
MAX
MAX
SINθ
Output Voltage
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
Power Required
-V
MAX
S3-S2 = V
S2-S1 = V
MAX
SIN(θ
+ 120°)
Notes:
(1) Pin programmable for SD-14590 only; SD-14591 is 14 bits and
SD-14592 is 16 bits.
(2) See TABLE 6.
(3) See Logic Input/Output section.
MAX
SIN(θ
+ 240°)
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
+V
S2-S4 = V
MAX
MAX
COS
θ
The circuit shown in FIGURE 1, the SD-14590/91/92 block dia-
gram, consists of three main parts: the signal input; a feedback
loop whose elements are the control transformer, demodulator,
error processor, VCO and up-down counter; and digital interface
circuitry including various latches and buffers.
In Phase with
RH-RL of Converter
and R2-R4 of RX.
INTRODUCTION
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
-V
MAX
S1-S3 = V
MAX
SIN(θ)
SIGNAL INPUTS
The SD-14590/91/92 series offer three input options: synchro,
resolver, and direct. In a synchro or resolver mode, shaft angle
data is transmitted as the ratio of carrier amplitudes across the
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
3
FOR 90 V SYNCHRO INPUTS
CR1
S1
CR2
S3
S3
RH
CR3
S2
RL
S1
HYBRID
1N6071A
inated. The synthesized reference circuit also eliminates the 180°
false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Error = Quad/Full Scale (FS) signal * tan(α)
Where: Error is in radians
Quad/FS signal is per unit quadrature input level.
α
= signal to reference phase shift in degrees.
S2
CR1, CR2, and CR3 are 1N6068A, bipolar transient voltage suppressors
or equivalent.
FOR 90 V RESOLVER INPUTS
S1
S2
90 V L-L
RESOLVER
INPUT
S3
S4
CR4
CR5
S3
S4
S1
S2
HYBRID
1N6071A
CR4 and CR5 are 1N6068A, bipolar transient voltage suppressors or equivalent.
FIGURE 3. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
verter. The control transformer performs the following trigono-
metric computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
where
θ
is the angle representing the resolver shaft position, and
φ
is the digital angle contained in the up/down counter. The track-
ing process consists of continually adjusting
φ
to make (θ -
φ)
=
0, so that
φ
will represent the shaft position
θ.
The output of the
demodulator is an analog DC level proportional to sin(θ -
φ).
The
error processor receives its input from the demodulator and inte-
grates this sin(θ -
φ)
error signal which then drives a Voltage
Controlled Oscillator (VCO). The VCO’s clock pulses are accu-
mulated by the up/down counter. The velocity voltage accuracy,
linearity and offset are determined by the quality of the VCO.
Functionally, the up/down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a Type II tracking servo. In a Type II servo, the VCO
always settles to a counting rate which makes dφ/dt equal to
dθ/dt without a lag. The output data will always be fresh and
available as long as the maximum tracking rate of the converter
is not exceeded.
A typical example of the magnitude of this source of error is as
follows:
Quad/FS signal = .001
α
=6
Error = 0.35 min
≈1
LSB in the 16th bit.
Note: Quad/FS is composed of static quadrature which is speci-
fied by the resolver or synchro supplier plus the speed voltage
which is given by:
Speed Voltage = rotational speed/carrier frequency
Where: Speed Voltage is the per unit ratio of electrical
rotational speed in RPS divided by carrier frequency in Hz.
This error is totally negligible for 14-bit converters. For 16-bit con-
verters where the highest accuracy possible is needed and
where the quadrature and phase shift specifications can be high-
er, this source of error could be significant. The reference syn-
thesizer circuit in the converter which derives the reference from
the input signal essentially sets
α
to zero resulting in complete
rejection of the quadrature.
DIGITAL INTERFACE
The digital interface circuitry has three main functions: to latch
the output bits during an inhibit command so that the stable data
can be read; to furnish both parallel and three-state data formats;
and to act as a buffer between the internal CMOS logic and the
external TTL logic.
In the SD-14590, applying an inhibit command will lock the data
in the transparent latch without interfering with the continuous
tracking of the feedback loop. Therefore, the digital angle is
always updated, and the inhibit can be applied for an arbitrary
amount of time. The inhibit transparent latch and the 50 ns delay
are part of the inhibit circuitry. The inhibit circuitry is described in
detail in the logic input/output section.
SYNTHESIZED REFERENCE
The synthesized reference section of the SD-14590 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals lead the reference signal
(RH and RL) by about 6°. When an uncompensated reference
signal is used to demodulate the control transformer’s output,
quadrature voltages are not completely eliminated. In a 14-bit
converter it is not necessary to compensate for the reference
signal’s phase shift. A 6° phase shift will, however, cause prob-
lems for the one minute accuracy converters. As shown in FIG-
URE 1, the converter synthesizes its own cos(ωt +
α)
reference
signal from the sinθcos(ωt +
α),
cosθcos(ωt +
α)
signal inputs
and from the cosωt reference input. The phase angle of the syn-
thesized reference is determined by the signal input. The refer-
ence input is used to choose between the +180° and -180° phas-
es. The synthesized reference will always be exactly in phase
with the signal input, and quadrature errors will therefore be elim-
LOGIC INPUT/OUTPUT
Logic angle outputs consist of 14 or 16 parallel data bits and
CONVERTER BUSY (CB). All logic outputs are short-circuit
proof to ground and +5 Volts. The CB output is a positive, 0.4 to
2.0 µs pulse. Data changes about 50 ns after the leading edge of
the pulse because of an internal delay. Data is valid 0.2 µs after
the leading edge of CB, the angle is determined by the sum of
the bits at logic “1.” Digital outputs are three-state and two bytes
wide. For 14 bit only: 1-6 (MSB’s) are enabled by signal EM, bits
7-14 (LSB’s) are enabled by the signal EL; for 14/16 program-
4
mable: 1-8 (MSB’s) are enabled by signal EM, 9-14 (LSB’s 14 bit)
or 9-16 (LSB’s 16 bit) are enabled by the signal EL. Outputs are
valid (logic “1” or “0”) 150 ns max after setting EM or EL low, and
are high impedance within 100 ns max of setting EM or EL high.
Both EM and EL are internally pulled-down to +5 V at 30 µA max.
The inhibit (INH) input locks the transparent latch so the bits will
remain stable while data is being transferred (See FIGURE 1).
The output is stable 0.5 µs after INH is driven to logic “0,” see FIG-
URE 4. A logic “0” at the T input latches the data, and a logic “1”
applied to T will allow the bits to change. The inhibit transparent
latch prevents the transmission of invalid data when there is an
overlap between CB and INH. While the counter is not being
updated, CB is at logic “0” and the INH latch is transparent.
When CB goes to logic “1,” the INH latch is locked. If CB occurs
after INH has been applied, the latch will remain locked and its
data will not change until CB returns to logic “0.” If INH is applied
during CB, the latch will not lock until the CB pulse is over. The
purpose of the 50 ns delay is to prevent a race condition between
CB and INH where the up-down counter begins to change as an
INH is applied. Whenever an input angle change occurs, the
converter changes the digital angle in 1 LSB steps and gener-
ates a converter busy pulse. Output data change is initiated by
the leading edge of the CB pulse, delayed by 50 ns, nominal.
Valid data is available at the outputs 0.2 µs after the leading
edge of CB, see FIGURE 5.
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
180
90
45
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
DEG/BIT
10,800
5,400
2,700
1,350
675
387.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
MIN/BIT
Note: EM enables the MSBs and EL enables the LSBs.
ing a large step and reset after the converter settles out. BIT will
also change to logic 1 for an over-velocity condition, because the
converter loop cannot maintain input-output and/or if the con-
verter malfunctions where it cannot maintain the loop at a null.
BIT will also be set if a total Loss-of-Signal (LOS) and/or a Loss-
of-Reference (LOR) occurs.
DYNAMIC PERFORMANCE
RESOLUTION CONTROL
Resolution control is via one logic input A. The SD-14590 (not
the SD-14591 or SD-14592) has programmable resolution.
A Type II servo loop (Kv =
∞)
and very high acceleration con-
stants give the SD-14590 superior dynamic performance, as list-
ed in TABLE 3. If the power supply voltages are not the ±15 VDC
nominal values, the specified input rates will increase or
decrease in proportion to the fractional change in voltage. A
Control Loop Block Diagram is shown in FIGURE 6, and an
Open Loop Bode Plot is shown in FIGURE 7. The values of the
transfer function coefficients are shown in TABLE 3.
An inhibit input, regardless of its duration, does not affect the
converter update. A simple method of interfacing to a computer
asynchronously to CB is: (A) apply the inhibit, (B) wait 0.5 µs
minimum, (C) transfer the data and (D) release the inhibit.
As long as the converter maximum tracking rate is not exceed-
ed, there will be no lag in the converter output. If a step input
BUILT-IN-TEST
The Built-ln-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero. If it exceeds approxi-
mately 65 LSBs (of the selected resolution), the logic level at BIT
will change from a logic 0 to logic 1. This condition will occur dur-
ASYNCHRONOUS TO CB
INH
DATA
FIGURE 4. INHIBIT TIMING DIAGRAM
6.1
µs
MIN
DEPENDS ON dφ/dt
;; ;;
;; ;;
0.5
µs
VALID
2.75
ERROR PROCESSOR
INPUT
θ
+
-
CT
e
A
1
S + 1
B
S S +1
10B
VCO
A
2
S
VELOCITY
OUT
DIGITAL
POSITION
OUT
(φ)
CB
0.2
µs
DATA
FIGURE 5. CONVERTER BUSY TIMING DIAGRAM
; ;
0.4-2.0
µs
VALID
H=1
A
2
Open Loop Transfer function = Output
S
2
S+ 1
B
S +1
10B
WHERE:
A
2
= A
1
A
2
FIGURE 6. CONTROL LOOP BLOCK DIAGRAM
5
FPGA/CPLD
