SD-14595/96/97 Datasheet
Make sure the next
Card you purchase
has...
®
SYNCHRO/RESOLVER-TO-DIGITAL
CONVERTERS
FEATURES
•
Single +5 V Power Supply
•
Accuracy to 1.3 Arc Minutes
•
Pin Programmable 14 Bit/16 Bit,
14 Bit Only or 16 Bit Only
•
No 180° False Lock-up
•
Internal Synthesized Reference
•
Built-In-Test (BIT) Output
•
Pin-for-Pin Replacement for
Natel’s 1044 and 1046, alternate
for Natel’s 1006 and 1056
DESCRIPTION
The SD-14595 is a low-cost, high reliability, synchro- or resolver-to-
digital converter with 14-bit-only, 16-bit-only or pin programmable
14-bit or 16-bit resolution. Packaged in a 36-pin DDIP, the
SD-14595/96/97 series feature Built-In-Test (BIT) output.
The SD-14595/96/97 series converters replace many discontinued
Natel units. Other features are solid-state signal and reference isola-
tion with high common mode rejection. In addition, the SD-14596 and
SD-14597 are pin-for-pin replacements for the Natel 1044 and 1046,
respectively.
The digital angle output from the SD-14595/96/97 is a natural binary
code, parallel positive logic and is TTL/CMOS compatible. The
SD-14595/96/97 accomplishes synchronization to a computer with
the Converter Busy (CB) output and/or the Inhibit (INH) input.
APPLICATIONS
Because of its high reliability, small size, and low power consumption,
the SD-14595/96/97 is ideal for military ground or avionics applica-
tions. All models are available with MIL-PRF-38534 processing.
Designed with three-state output, the SD-14595/96/97 is especially
well-suited for use with computer based systems. Among the many
possible applications are radar and navigation systems, fire control
systems, flight instrumentation, and flight trainers or simulators.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1997, 1999 Data Device Corporation
SOLID STATE SYNCHRO INPUT OPTION
SIN
q
COS
q
RESOLVER
CONDITIONER
COS
q
COS
q
VOLTAGE
FOLLOWER
BUFFER
COS
q
INTERNAL
DC
REFERENCE
SIN
q
SIN
q
SIN
q
SOLID STATE RESOLVER INPUT OPTION
DIRECT INPUT OPTION
S1
ELECTRONIC
SCOTT T
S2
V
REF IN
RH
RL
BIT
Data Device Corporation
www.ddc-web.com
S1
S2
S3
S4
INPUT OPTIONS
REFERENCE
CONDITIONER
LOS
R
SYNTHESIZED
REF
BIT DETECT
VEL
LOS
SIN
q
COS
q
SIN
(q-f)
1 LSB ANTIJITTER FEEDBACK
16 BIT CT
TRANSPARENT
LATCH
CB
HIGH
ACCURACY
CONTROL
TRANSFORMER
GAIN
e
DEMODULATOR
D
VEL
ERROR
PROCESSOR
T
e
VCO
U
E
DIGITAL
ANGLE
f
U
16 BIT
UP/DOWN
COUNTER
T
INH
50 ns DELAY
Q
INHIBIT
TRANSPARENT
LATCH
+8.6 V
ANALOG RETURN
V(+4.3 V)
V
14B
BITS 1-8
BITS 9-16 LBE
RESOLUTION (14595 ONLY)
CONTROL
VOLTAGE
DOUBLER
+5 V
INH
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
T
EDGE
TRIGGERED
LATCH
S3
INPUT OPTION
2
3 STATE
TTL BUFFER
HBE
SD-14595/6/7
G-06/09-0
FIGURE 1. sd-14595/96/97 BLOCK dIAGRAM
Specifications apply over temperature range, power supply range, reference fre-
quency, and amplitude range; 15% signal amplitude variation, up to 10% harmon-
ic distortion in the reference, and up to 45° of signal to reference phase shift.
TABLE 1. sd-14595/96/97 sPECIFICATIONs
TABLE 1. sd-14595/96/97 sPECIFICATIONs (CONT)
PARAMETER
dIGITAL INPUT/OUTPUT
(cont)
Resolution Control (14B)
(for Programmable Units Only)
UNIT
VALUE
PARAMETER
REsOLUTION
ACCURACY
REPEATABILTY
REFERENCE INPUT
CHARACTERIsTICs
Carrier Frequency Range
Voltage Range
UNIT
Bits
Min
LSB
VALUE
14 or 16
1,2,4 + 1LSB
1 Max
Enable Bits 1 to 8 (HBE)
Enable Bits 9 to 16 (LBE)
(9 to 14 for 14-bit mode)
Hz
Hz
Vrms
47-1000 (60 Hz Unit)
360-1000 (400 Hz Unit)
4-130 (for 11.8 V or 90 V
signal input)
3-100 (for 1 V direct signal
input)
250k min
500k min
250 peak max
Logic 1 for 14 bits
Logic 0 for 16 Bits
Pull-up current source to
+5 V || 5 pF max CMOS
transient protected
Logic 0 enables
Data Valid within 150 ns
Logic 1 = High Z
Data High Z within 100 ns
Pull-down current source
to GND || 5 pF max CMOS
transient protected
Bits
14 or 16 parallel lines;
natural binary angles, posi-
tive logic (see TABLE 3)
0.8 to 3.0 µs positive pulse;
leading edge initiates coun-
ter update.
Logic 1 for fault conditions.
50 pF + rated logic drive
Logic 0; 1 TTL load,
1.6 mA at 0.4 V max
Logic 1; 10 TTL loads,
0.4 mA at 2.8 V min High
Z;10 µA || 5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply
minus 100 mV min
driving CMOS
+4.3 V nom
See TABLE 4
Outputs:
Parallel Data
Input Impedance:
Single Ended
Differential
Common Mode Range
sIGNAL INPUT
CHARACTERIsTICs
(voltage options and minimum
input impedance)
Input Impedance Imbalance
Synchro
• Zin Line-to-Line
• Zin Each Line-to-Gnd
• Common Mode Range
• Maximum Transient Peak
Voltage
Resolver
• Zin Single Ended
• Zin Differential
• Zin Each Line-to Gnd
• Common Mode Range
• Maximum Transient Peak
Voltage
Direct (1.0 V L-L)
• Input Signal Type
• Sin/Cos Voltage Range
• Max Voltage w/o Damage
• Input Impedance
REFERENCE
sYNTHEsIZER
± Sig/Ref Phase Shift
dIGITAL INPUT/OUTPUT
Logic Type
Inputs:
Inhibit (INH)
Ohm
Ohm
V
Converter Busy (CB)
BIT
Drive Capability
%
V
Ohm
Ohm
Vpeak
V
V
Ohm
Ohm
Ohm
V
V
0.2 max
11.8 V L-L 90 V L-L
17.5k
130k
11.5k
85k
30
180
150
11.8 V L-L
23k
46k
23k
60 max
150
Sin and Cos resolver sig-
nals referenced to con-
verter internal DC refer-
ence V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M || 10 pf voltage
follower
60 typ, 45 guaranteed
ANALOG OUTPUT
Analog Return (V)
Velocity (VEL)
(polarity is negative voltage for
positive angular rate)
AC error (e)
14-Bit Mode
16-Bit Mode
Load
dYNAMIC CHARACTERIsTICs
POWER sUPPLY
CHARACTERIsTICs
Nominal Voltage
Voltage Tolerance
Max Voltage w/o damage
Current
TEMPERATURE
RANGEs
Operating (-1XX or -4XX)
(-2XX or 5XX)
(-3XX or -8XX)
Storage
PHYsICAL CHARACTERIsTICs
mVrms
mVrms
mA
3.5 per LSB of error
1.75 per LSB of error
1
See TABLE 6
Vrms
Ohm
Deg
V
%
V
mA
+5
±10
+7
35 max+digital output load
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 µA max
Logic 0 inhibits Data sta-
ble within 0.5 µs (pull up)
°C
°C
°C
°C
in
(mm)
oz(g)
-55 to +125
-40 to +85
0 to 70
-65 to +150
.9 x 0.78 x 0.21
(48 x 20 x 5.3 )
36-Pin Double Dip
0.7 max (20)
Data Device Corporation
www.ddc-web.com
3
SD-14595/6/7
G-06/09-0
TABLE 1. sd-14595/96/97 sPECIFICATIONs (CONT)
PARAMETER
TRANsFORMER
CHARACTERIsTICs
(See ordering information for list
of Transformers. Reference
Transformers are Optional for
Both Solid-State and Voltage
Follower Input Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
Signal Transformer
Carrier Frequency Range
Breakdown Voltage to GND
Minimum Input impedances
(Balanced)
90 V L-L
26 V L-L
11.8 V L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
Output Voltage
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
Output Voltage
Power Required
VALUE
Converter operation
As shown in FIGURE 1, the converter section of the
SD-14595/96/97 contains a high accuracy control transformer,
demodulator, error processor, voltage controlled oscillator (VCO),
up-down counter, and reference conditioner. The converter pro-
duces a digital angle which tracks the analog input angle to
within the specified accuracy of the converter.The con trol trans-
former performs the following trigonometric computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
360-1000 Hz
700 V peak
SynchroZ
in
(Z
so
) Resolver Z
in
100 kΩ
-
20 kΩ
100 kΩ
30 kΩ
30 kΩ
Where:
θ
is angle theta representing the resolver shaft posi-
tion.
φ
is digital angle phi contained in the up/down counter.
The tracking process consists of continually adjusting
φ
to make
(θ -
φ)
= 0, so that
φ
will represent the shaft position
θ.
The output of the demodulator is an analog dc level proportional
to sin(θ -
φ).
The error processor receives its input from the
demodulator and integrates this sin(θ -
φ)
error signal which then
drives the VCO. The VCO’s clock pulses are accumulated by the
up/down counter. The velocity voltage accuracy, linearity and
offset are determined by the quality of the VCO. Functionally, the
up/down counter is an incremental integrator. Therefore, there
are two stages of integration which makes the converter a Type II
tracking servo.
In a Type II servo, the VCO always settles to a counting rate
which makes dφ/dt equal to dθ/dt without lag. The output data will
always be fresh and available as long as the maximum tracking
rate of the converter is not exceeded.
The reference conditioner is a comparator that produces the
square wave reference voltage which drives the demodulator. It’s
single ended Input Z is 250k ohms/min, 500k ohms differential.
47 - 440 Hz
80 -138 V rms; 115 V rms
nominal resistive
600 kΩ min, resistive
500 V rms transformer isolated
+R (in phase with RH-RL) and -R
(in phase with RL- RH) derived
from op-amps. Short-Circuit proof.
3.0 V nominal riding on ground ref-
erence V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
47 - 440 Hz
10 -100 V rms L- L; 90 V rms
L- L nominal
148 kΩ min L- L balanced
resistive
±500 V rms, transformer isolated
Resolver output,
- sine (- S) + Cosine (+C) derived
from op-amps. Short circuit proof.
1.0 V rms nominal riding on ground
reference V. Output voltage level
tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
sPECIAL FUNCTIONs
referenCe SyntheSizer-Quadrature voltageS.
The synthesized reference section of the SD-14595 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals typically lead the refer-
ence signal (RH and RL) by about 6°. When an uncompensated
reference signal is used to demodulate the control transformer’s
output, quadrature voltages are not completely eliminated. In a
14-bit converter it is not necessary to compensate for the refer-
ence signal’s phase shift. A 6° phase shift will, however, cause
problems for the one minute accuracy converters. As shown in
FIGURE 1, the converter synthesizes its own cos(ωt +
α)
refer-
ence signal from the sinθ - cos(ωt +
α),
cosθ - cos(ωt +
α)
signal
inputs and from the cosωt reference input. The phase angle of the
synthesized reference is determined by the signal input. The ref-
erence input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
phase with the signal input, and quadrature errors will therefore
be eliminated.
The synthesized reference circuit also elimi-
nates the 180° false error null hangup.
THEORY OF OPERATION
The SD-14595/96/97 series are small, 36-pin DDIP synchro-to-
digital hybrid converters. As shown in the block diagram (FIGURE
1), the SD-14595/96/97 can be broken down into the following
functional parts: Signal Input Option, Converter, Analog
Conditioner, Power Supply Conditioner, and Digital Interface.
Data Device Corporation
www.ddc-web.com
4
SD-14595/6/7
G-06/09-0
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/Full Scale (FS).signal) •
tan(α)
Where:
Magnitude of Error is in radians.
Quadrature Voltage is in volts.
Full Scale signal is in volts.
α
= signal to REF phase shift
An example of the magnitude of error is as follows:
Let:
Quadrature Voltage = 11.8 mV
Let:
FS signal = 11.8 V
Let:
α
= 6°
Then: Magnitude of Error = 0.35 min
≅
1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed volt-
age which is determined by the following formula:
Speed Voltage=(rotational speed/carrier frequency) • FS signal
Where:
Speed Voltage is the quadrature due to rotation.
Rotational speed is the rps (rotations per second) of the
synchro or resolver.
Carrier frequency is the REF in Hz.
Built-in-teSt (Bit, pin 15)
The Built-In-Test output (BIT) monitors the level of error from the
demodulator output (D). (D) is the difference in the input and
output angles and ideally should be zero when the converter
error is null. If (D) exceeds the static threshold of approximately
180 LSbs (of the selected resolution) the logic level at BIT will
change from a logic 0 to logic 1.
This "Excessive Error" condition may also occur during a large
step event, but is dependent on the settling time and magnitude
of the step. It may also be triggered by errors associated with a
constant acceleration. BIT will reset after (D) is within 180
LSbs.
BIT will also change to logic 1 for an over-velocity condition,
where the converter loop cannot maintain input to output tracking
and/or if the converter malfunctions where it cannot maintain the
loop at a null.
BIT will also be set for a Loss-of-Signal (LOS) and/or a Loss-of-
Reference (LOR).
programmaBle reSolution (14B, pin 16)
Resolution is controlled by one logic input,14B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
insure that a race condition does not exist between counting and
changing the resolution, input 14B is latched internally on the
trailing edge of CB (see FIGURE 2).
Note: The SD-14595 has programmable resolution whereas the
SD-14596 and 97 do not.
INTERFACING - INPUTs
Signal input optionS
The SD-14595/96/97 series offers direct synchro or resolver
inputs. In a synchro or resolver, shaft angle data is transmitted as
the ratio of carrier amplitudes across the input terminals. Synchro
signals, which are of the form sinθcosωt, sin(θ+120°) cosωt, and
sin(θ+240°)cosωt are internally converted to resolver format,
sinθcosωt and cosθcosωt.
FIGURE 3 illustrates synchro and resolver signals as a function
of the angle
θ.
The solid-state signal and reference inputs are true differential
inputs with high ac and dc common mode rejection.
Input imped-
ance is maintained with power off.
S1-S3 = V
MAX
MAX
SIN
+V
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
CCW
(DEGREES)
-V
MAX
S3-S2 = V
S2-S1 = V
SIN(
MAX
SIN(
MAX
Standard
From Electrical Zero (EZ).
Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
+V
MAX
S2-S4 = V
MAX
COS
In Phase with
RH-RL of Converter
and R2-R4 of RX.
0
360
30
90
150
210
270
330
CCW
(DEGREES)
CB
0 s MIN
0.1 s MIN
14B
-V
MAX
S1-S3 = V
MAX
SIN(
Standard Resolver Control
from Electrical
(RX)
(EZ) with R2-R4 Excited.
of CCW Rotation
Rotation
Transmitter
Zero
Outputs as a Function
From Electrical Zero (EZ) With R2-R4 Excited.
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
FIGURE 2. REsOLUTION CONTROL TIMING dIAGRAM
Data Device Corporation
www.ddc-web.com
5
FIGURE 3. sYNCHRO ANd REsOLVER sIGNALs
SD-14595/6/7
G-06/09-0
DSP 与 ARM 处理器
