These specifications apply over temperature range, power supply range, reference frequency, and amplitude range
+10% signal amplitude variation and up to 10% harmonic distortion in the reference.
PARAMETER
RESOLUTION
ACCURACY GRADES
DIFFERENTIAL LINEARITY
REPEATABILITY
REF INPUT CHARACTERISTICS
Voltage Range
Carrier Frequency Ranges
10, 12, or 14 bit
16 bit
Input Impedance
Single Ended Input
Differential
Common Mode Range
SIGNAL INPUT CHARACTERISTICS
Synchro
Zin Line to Line
Zin Each line to ground
Common Mode Range
Resolver
Zin Single Ended
Zin Differential
Zin Each line to ground
Common Mode Range
Direct (2.0 V L-L)
Input Signal Type
sin/cos Range
Max Voltage Without Damage
Input lmpedance
REFERENCE SYNTHESIZER
±Sig/Ref Phase Shift
DIGITAL INPUTS
Logic Type
Inputs
Max Input Voltage w/o Damage
Loading
INH (Inhibit)
EN (Enable bits 1-8) and
EL (Enable bits 9-16)
S (Control Transformer)
Resolution Control
10 Bit
12 Bit
14 Bit
16 Bit
DIGITAL OUTPUTS
Parallel Data
CB (Converter Busy)
BIT
(Built-ln-Test)
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
60° typ, 45° min
2 Vrms nom, 2.2 Vrms max
15 V CONTINUOUS,
100 V PEAK TRANSIENT
Zin > 20M//10 pF
Sin and cos resolver signals referenced to converter internal DC reference voltage, V.
11.8 V L-L
17.5 kOhm
11.5 kOhm
60 V max
11.8 V L-L
23 kOhm
46 kOhm
23 kOhm
60 V max
50 kOhm min
100 kOhm min
50 V peak max
200 V transient peak
Voltage options and minimum input impedance balanced.
1-5 kHz (full accuracy)
2-5 kHz
Up to 10 kHz with reduced accuracy.
1-35 Vrms
TABLE 1. SDC-14580 SPECIFICATIONS
VALUE
COMMENT
Pin Programmable.
Max +1 LSB of selected resolution, see TABLE 8 and Ordering Information
10, 12, 14, or 16 bits
±4, ±2, or ±1 minutes
1 LSB max in the 16th bit
1 LSB max
TTL/CMOS compatible.
-0.3 Vdc to +8 Vdc
10 µA max
Pull-up current source to +5 V//5 pF max, CMOS transient protected.
Logic 0 inhibits, Logic 1 enables, Data stable within 0.3 µs.
Logic 0 enables, Logic 1 high Z within 100 ns, Data valid within 150 ns.
Logic 0 for Control Transformer, Logic 1 for normal tracking.
B (pin 36)
0
0
1
1
A (pin 35)
0
1
0
1
Unused output bits are at logic 0.
10, 12, 14, or 16 bits
0.4 µs to 1.0 µs
Natural binary angle positive logic.
Positive pulse; leading edge indicates counter update.
Logic 0 for
BIT
condition.
Data Device Corporation
www.ddc-web.com
3
SDC-14580
J-1/10-0
These specifications apply over temperature range, power supply range, reference frequency, and amplitude range;
+10% signal amplitude variation and up to 10% harmonic distortion in the reference.
PARAMETER
DIGITAL OUTPUTS (CONTIN-
UED)
Drive Capability
50 pF plus rated logic drive.
Logic 0
Logic 1
Logic 0
Logic 1
High Z
ANALOG OUTPUTS (NOTE 1)
VEL (Velocity)
e (AC error)
10 bit mode
12 bit mode
14 bit mode
16 bit mode
Load
DYNAMIC CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS (NOTE 1)
Nominal Voltage and Range
Max Voltage w/o Damage
Max Current
TEMPERATURE RANGES
Operating
-30X
-10X
Storage
PHYSICAL CHARACTERISTICS
Size
Weight
VALUE
COMMENT
TABLE 1. SDC-14580 SPECIFICATIONS (CONTINUED)
-1.6 mA at 0.4 V max
0.4 mA at 2.8 V min
100 mV max
+5 V supply minus 100 mV min
10 µA//5 pF max
1 TTL Load
10 TTL Loads
driving CMOS
driving CMOS
See TABLE 5, Velocity Characteristics.
50 mVrms
25 mVrms
12.5 mVrms
6.3 mVrms
3 kOhm min
per
per
per
per
LSB
LSB
LSB
LSB
of
of
of
of
error
error
error
error
See TABLE 7, Dynamic Characteristics.
+15 Vdc ±5%
+18 V
25 mA
+5 Vdc ±10%
+8 V
10 mA
-15 Vdc ±5%
-18 V
15 mA
0 °C to +70 °C
-55 °C to +125 °C
-65 °C to +150 °C
36 pin DDIP
1.9 x 0.78 x 0.21 inches
(48.3 x 19.8 x 5.3 mm)
0.7 oz (20 gm)
Notes:
1. It is recommended to place 0.1uF external bypass capacitors on the ±15V supplies for higher noise immunity on the analog Velocity and AC error (e) outputs.
TABLE 2. MAXIMUM RATINGS WITHOUT DAMAGE
PARAMETER
Reference Inputs
Direct signal Inputs
Digital Inputs
Supply Voltage
Storage Temperature
Lead Temperature (soldering, ten seconds)
Thermal Resistance:
Junction to Case (θ
jc
)
Case to Ambient (θ
ca
)
+15 Vdc
+18 V
VALUE
130 Vrms
15 V continuous,
100 V peak transient
-0.3 Vdc to +8 Vdc
+5 Vdc
+8 V
-65 °C to 150 °C
300 °C
8 °C/W
20 °C/W
-15 Vdc
-18 V
ALL POWER (I.E., POWER SUPPLY AND
SIGNAL INPUTS) SHOULD BE REMOVED
FROM THE CIRCUIT WHEN ADDING OR
REMOVING THE CONVERTER.
COMMENT
Data Device Corporation
www.ddc-web.com
4
SDC-14580
J-1/10-0
THEORY OF OPERATION
The SDC-14580 Series are small, 36 pin DDIP Synchro-to-Digital
or Resolver-to-Digital hybrid converters. As shown in the block
diagram (FIGURE 1), the SDC-14580 can be broken down into
the following functional parts: Signal Input Option, Converter,
Analog Conditioner, Power Supply Conditioner, and Digital
Interface.
CONVERTER OPERATION
As shown in FIGURE 1, the converter section of the SDC-14580
contains a high accuracy control transformer, demodulator, error
processor, voltage controlled oscillator (VCO), up-down counter,
and reference conditioner. The converter produces a digital
angle which tracks the analog input angle to within the specified
accuracy of the converter.
The control transformer performs the following trigonometric
computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
12- or 14-bit converter it is not necessary to compensate for the
reference signal’s phase shift. A 6° phase shift will, however,
cause problems for the one minute accuracy converters. As
shown in FIGURE 1, the converter synthesizes its own cos(ωt+α)
reference signal from the sinθ-cos(ωt+α), cosθ-cos(ωt +α) signal
inputs and from the cosωt reference input. The phase angle of
the synthesized reference is determined by the signal input. The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
phase with the signal input, and quadrature errors will therefore
be eliminated.
The synthesized reference circuit also elimi-
nates the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/F.S.signal) • tan(α)
Where:
θ
is angle theta representing the resolver shaft position.
φ
is digital angle phi contained in the up/down counter.
Where:
Magnitude of Error is in radians.
Quadrature Voltage is in volts.
Full Scale signal is in volts.
α
= signal to REF phase shift
An example of the magnitude of error is as follows:
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let:
α =
6°
Then: Magnitude of Error = 0.35 min
≅
1 LSB in the 16th bit.
Note:
In a Type II servo, the VCO always settles to a counting rate
which makes dφ/dt equal to dθ/dt without lag. The output data will
always be fresh and available as long as the maximum tracking
rate of the converter is not exceeded.
The reference conditioner is a comparator that produces the
square wave reference voltage which drives the demodulator. Its
single ended Input Z is 50k Ohms min, 100k Ohms differential.
Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the
speed voltage which is determined by the following for-
mula:
The tracking process consists of continually adjusting
φ
to make
(θ -
φ)
= 0, so that
φ
will represent the shaft position
θ.
The output of the demodulator is an analog DC level propor-
tional to sin(θ-φ). The error processor receives its input from the
demodulator and integrates this sin(θ -
φ)
error signal which then
drives the VCO. The VCO’s clock pulses are accumulated by the
up/down counter. The velocity voltage accuracy, linearity and
offset are determined by the quality of the VCO. Functionally, the
up/down counter is an incremental integrator. Therefore, there
are two stages of integration which makes the converter a Type
II tracking servo.
Speed Voltage=(rotational speed/carrier frequency) • F.S. signal
Where: Speed Voltage is the quadrature due to rotation.
Rotational speed is the RPS (rotations per second) of
the synchro or resolver.
Carrier frequency is the REF in Hz
BUILT-IN-TEST (BIT, PIN 34)
The Built-In-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero. If it exceeds approxi-
mately 65 LSBs (of the selected resolution), the logic level at BIT
will change from a logic 1 to logic 0. This condition will occur dur-
ing a large step and reset after the converter settles out. BIT will
5
SDC-14580
J-1/10-0
SPECIAL FUNCTIONS
REFERENCE SYNTHESIZER-QUADRATURE VOLTAGES
The synthesized reference section of the SDC-14580 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals typically lead the refer-
ence signal (RH and RL) by about 6°. When an uncompensated
reference signal is used to demodulate the control transformer’s
output, quadrature voltages are not completely eliminated. In a
模拟与混合信号
