SDN137
Digital High Speed Optocoupler
10MBd, Logic Output
Description
The SDN137 consists of a high efficient AlGaAs Light
Emitting Diode and a high speed optical detector. This
design provides excellent AC and DC isolation between the
input and output sides of the Optocoupler.
The output of the optical detector features an open
collector Schottky clamped transistor. The enable function
allows the optical detector to be strobed. The internal
shield ensures high common mode transient immunity. A
guaranteed common mode transient immunity is up to
15,000V/μS.
The SDN137 comes standard in an 8 pin DIP package.
Features
TTL Compatible
High Bit Rate: 10MBd
High CMR Performance (15kV/S)
High Isolation Voltage (5000V
RMS
)
High Common Mode Interference Immunity
RoHS / Pb-Free / REACH Compliant
Agency Approvals
UL / C-UL:
VDE:
File # E201932
File # 40035191 (EN 60747-5-2)
Applications
High Speed Logic Ground Isolation
Replace Slower Speed Optocouplers
Line Receivers
Power Transistor Isolation
Pulse Transformer Replacement
Switch Mode Power Supplies
Digital Fieldbus Isolation
Ground Isolation – Analog Signals
Absolute Maximum Ratings
The values indicated are absolute stress ratings. Functional
operation of the device is not implied at these or any
conditions in excess of those defined in electrical
characteristics section of this document. Exposure to
absolute Maximum Ratings may cause permanent damage
to the device and may adversely affect reliability.
Storage Temperature …………………………..-55 to +125°C
Operating Temperature …………………………-40 to +85°C
Continuous Input Current ………………………………..40mA
Transient Input Current ………………….……………..400mA
Reverse Input Control Voltage …………….………………5V
Max Enable Input Voltage (V
E
) …………………………….5V
Max Enable Input Current (I
E
) ……………..…………….5mA
Input Power Dissipation ……..…………………………40mW
Max Supply Voltage (V
CC
) …………………………………..7V
Max Output Collector Current (I
O
) ……..……………….50mA
Max Output Collector Voltage (V
O
) ...................................7V
Output Power Dissipation ……………………………..85mW
Schematic Diagram
NC 1
8 V
CC
Anode 2
7 V
E
Cathode 3
6 V
O
NC 4
5 Ground
Truth Table
(Positive Logic)
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
Ordering Information
Part Number
SDN137
SDN137-H
SDN137-S
SDN137-STR
Description
8 pin DIP, (50/Tube)
0.40” (
10.16mm
) Lead Spacing (
VDE0884
)
8 pin SMD, (50/Tube)
8 pin SMD, Tape and Reel (1000/Reel)
SCN137
** A 0.1μF bypass Capacitor must be connected between pins 5 & 8
(GND & V
CC
)
NOTE: Suffixes listed above are not included in marking on
device for part number identification
© 2012 Solid State Optronics
•
San José, CA
www.ssousa.com
•
+1.408.293.4600
Page # 1
SDN137/H/S/TR
Rev 1.10 (08/09/2012)
001512
SDN137
Digital High Speed Optocoupler
10MBd, Logic Output
Electrical Characteristics,
T
A
= 25°C (unless otherwise specified)
Parameter
Input Specifications
Input Forward Voltage
Input Forward Voltage Temp Coefficient
Input Reverse Voltage
Input Threshold Current
Input Capacitance
V
F
V
F
/T
BV
R
I
TH
C
IN
-
-
5
-
-
1.36
-1.5
-
1.1
34
1.70
-
-
5
-
V
mV/°C
V
mA
pF
I
F
= 10mA
I
F
= 10mA
I
R
= 10
A
V
E
=2V, VCC=5.5V, I
OL
(sinking)=13mA
f=1MHz, V
F
=0V
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Output Specifications,
V
CC
= 5V (unless otherwise specified)
High Level Supply Current
Low Level Supply Current
High Level Enable Current
Low Level Enable Current
High Level Enable Voltage
Low Level Enable Voltage
High Level Output Current
Low Level Output Voltage
I
CCH
I
CCL
I
EH
I
EL
V
EH
V
EL
I
OH
V
OL
-
-
-
-
2
-
-
-
7.4
10
-0.6
-0.9
-
-
-
0.28
10
13
-1.6
-1.6
-
0.8
100
0.60
A
V
V
E
=2V, V
CC
=5.5V, V
O
=5.5V, I
F
=250
A
V
E
=2V, VCC=5.5V, I
F
=5mA
I
OL
(sinking)=13mA
mA
mA
mA
mA
V
V
E
=0.5V, V
CC
=5.5V, I
F
=0mA
V
E
=0.5V, V
CC
=5.5V, I
F
=10mA
V
E
=2V
V
E
=0.5V
Switching Specifications,
V
CC
= 5V, I
F
=7.5mA (unless otherwise specified)
Propagation Delay Time to
Low Output Level
Propagation Delay Time to
High Output Level
Pulse Width Distortion
Propagation Delay Skew
Output Rise Time (10% - 90%)
Output Fall Time (90% - 10%)
Propagation Delay Time of enable from V
EH
to V
EL
Propagation Delay Time of enable from V
EL
to
V
EH
Logic High Common Mode Transient
Immunity
Logic Low Common Mode Transient
Immunity
t
PHL
t
PLH
| t
PLH
- t
PHL
|
t
PSK
t
r
t
f
t
ELH
t
EHL
|CM
H
|
|CM
L
|
25
25
-
-
-
-
-
-
5,000
5,000
35
45
10
8
20
8
22
12
-
-
100
100
35
40
-
-
-
-
-
-
nS
nS
nS
nS
nS
nS
nS
nS
V/S
V/S
R
L
=350, C
L
=15pF
R
L
=350, C
L
=15pF
R
L
=350, C
L
=15pF
R
L
=350, C
L
=15pF
R
L
=350, C
L
=15pF
R
L
=350, C
L
=15pF
R
L
=350, C
L
=15pF, V
EL
=0V, V
EH
=3V
R
L
=350, C
L
=15pF, V
EL
=0V, V
EH
=3V
|V
CM
|=20V, V
CC
=5V, I
F
=0mA, V
O (MIN)
=2V,
R
L
=350
|V
CM
|=20V, V
CC
=5V, I
F
=7.5mA, V
O (MIN)
=0V,
R
L
=350
© 2012 Solid State Optronics
•
San José, CA
www.ssousa.com
•
+1.408.293.4600
Page # 2
SDN137/H/S/TR
Rev 1.10 (08/09/2012)
001512
SDN137
Digital High Speed Optocoupler
10MBd, Logic Output
Electrical Characteristics, continued…
T
A
= 25°C (unless otherwise specified)
Parameter
Isolation Specifications
Input-Output Insulation Leakage Current
Withstand Insulation Test Voltage
Input-Output Resistance
Input-Output Capacitance
I
I-O
V
ISO
R
I-O
C
I-O
-
5000
-
-
-
-
10
12
Symbol
Min.
Typ.
Max.
1.0
-
-
-
Units
μA
V
RMS
pF
Test Conditions
45% RH, t=5s, V
I-O
=3kV
RH
≤
50%, t=1min
V
I-O
= 500V
DC
f=1MHz
1.0
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
A 0.1F or bigger bypass capacitor for V
CC
is needed as shown in Figure 1
Peaking driving circuit may be used to speed up the LED. The peak drive current of LED may go up to 50mA and maximum pulse width
50ns, as long as average current doesn’t exceed 20mA.
t
PLH
(propagation delay) is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of
the output pulse.
t
PHL
(propagation delay) is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of
the output pulse.
The t
ELH
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
rising edge of the output pulse.
The t
EHL
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
falling edge of the output pulse.
CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V
O
> 2.0 V).
CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V
O
<
0.8 V).
No external pull up is required for a high logic state on the enable input. If the enable pin is not used, tying it to V
CC
.
10. Device is considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
11. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V
RMS
for one second (leakage
current less than 5
A).
This test is performed before the 100% production test for partial discharge
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 V
RMS
for one second (leakage
current less than 5
A).
This test is performed before the 100% production test for partial discharge
Recommended Operating Conditions,
T
A
= 25°C (unless otherwise specified)
Parameter
Operating Temperature
Supply Voltage
Low Level Input Current
High Level Input Current
Low Level Enable Voltage
High Level Enable Voltage
Output Pull Up Resistor
Fan Out
Symbol
°C
V
CC
I
FL
I
FH
V
EL
V
EH
R
L
N
Min.
-40
4.5
0
5
0
2
330
-
Typ.
-
-
-
-
-
-
-
-
Max.
85
5.5
250
15
0.8
V
CC
4k
5
Units
°C
V
A
mA
V
V
-
Test Conditions
R
L
= 1k
© 2012 Solid State Optronics
•
San José, CA
www.ssousa.com
•
+1.408.293.4600
Page # 3
SDN137/H/S/TR
Rev 1.10 (08/09/2012)
001512
SDN137
Digital High Speed Optocoupler
10MBd, Logic Output
SDN137 Electrical Test Circuits
Figure 1:
Single Channel Test Circuit for t
PHL
and t
PLH
Figure 2:
Single Channel Test Circuit for t
EHL
and t
ELH
Figure 3:
Single Channel Test Circuit for Common Mode Transient Immunity
© 2012 Solid State Optronics
•
San José, CA
www.ssousa.com
•
+1.408.293.4600
Page # 4
SDN137/H/S/TR
Rev 1.10 (08/09/2012)
001512
SDN137
Digital High Speed Optocoupler
10MBd, Logic Output
SDN137 Performance & Characteristics Plots,
T
A
= 25°C (unless otherwise specified)
Figure 4:
Input Diode Forward Characteristics
1.5
T
A
=25°C
V
F
- Input Forword Voltage (V)
Figure 5:
Input Diode Forward Voltage vs. Temperature
2
T
A
=25°C
1.8
V
F
- Forword Voltage (V)
1.45
1.4
1.35
1.3
1.25
1.2
0
5
10
15
20
25
30
I
F
- Input Forword Current (mA)
I
F
=20mA
1.6
DPlot
Trial
Version
http://www.dplot.com
1.4
DPlot
Trial
Version
http://www.dplot.com
I
F
=2mA
I
F
=10mA
0
20
40
60
80
100
I
F
=30mA
1.2
1
-40
-20
T
A
- Ambient Temperature (C)
Figure 6:
Input Diode Threshold Current vs. Temperature
3
I
TH
- Input Threshold Current (mA)
Figure 7:
Output Voltage vs. Input Forward Current
6
2.5
2
1.5
1
0.5
0
-40
Vcc=5.0V
Vo=0.6V
5
Vcc=5V
T
A
=25°C
RL=4k
DPlot
Trial
RL=4k
Version
http://www.dplot.com
RL=1k
RL=350
Vo - Output Voltage (V)
4
3
2
1
0
DPlot
Trial
RL=350
Version
http://www.dplot.com
RL=1k
-20
0
20
40
60
80
100
0
1
2
3
4
5
6
T
A
- Ambient Temperature (C)
I
F
- Input Forword Current (mA)
Figure 8:
Low Level Output Voltage vs. Temperature
0.6
I
OL
- Low Level Output Current (mA)
V
OL
- Low Level Output Voltage (V)
Figure 9:
Low Level Output Current vs. Temperature
65
0.5
I
OL
=16mA
0.4
0.3
0.2
0.1
0
-40
Vcc=5.5V
V
E
=2.0V
I
F
=5mA
I
OL
=13mA
60
Vcc=5.0V
V
E
=2.0V
V
OL
=0.6V
DPlot
Trial
Version
http://www.dplot.com
I
OL
=6.4mA
I
OL
=9.6mA
55
50
DPlot
I
F
=10-15mA
Trial
Version
http://www.dplot.com
I
F
=5mA
45
-20
0
20
40
60
80
100
T
A
- Ambient Temperature (C)
40
-40
-20
0
20
40
60
80
100
T
A
- Ambient Temperature (C)
© 2012 Solid State Optronics
•
San José, CA
www.ssousa.com
•
+1.408.293.4600
Page # 5
SDN137/H/S/TR
Rev 1.10 (08/09/2012)
001512
