SED1278
OVERVIEW
The SED1278 is a dedicated character display controller/
driver which, when used with the SED1181F or the
SED1681 segment drivres, is able to display up to 80
characters under 4- or 8-bit MPU control.
The internal character generator (CG) ROM has an
extended 240, 5×10 pixel, character set, plus CGRAM
space for an additional eight user definable 5×8 pixel
characters. These memory features combined with the
rich set of control instructions offer the potential for a
highly flexible character display system.
The SED1278 features a guaranteed minimum LCD
drive voltage of 3 V making it suitable for use with low
voltage LCD panels.
FEATURES
• Interface for 4- and 8-bit MPUs
• Display RAM – 80 bytes (80 characters)
• Character generator ROM – 240 characters
– 5×8 pixel font
• Character genrator RAM – 64 bytes
– 5×8 pixel font, 8 characters.
– 5×10 pixel font, 4 characters.
• Number of characters used
Duty SED1278F SED1181F
LA
One-line 1/8,
display
1/11
1
0
6
Two-line 1/16
display
1
0
3
No. of
characters used
8 columns
×
1 line
80 columns
×
1 line
8 columns
×
2 lines
40 columns
×
2 lines
• Powerful display control instructions
• LCD driver outputs
– 40 segment driver outputs
– 16 common driver outputs
• Low LCD drive voltage – 3 V minimum (V
DD
–V
5
)
• Dual-frame AC drive
• On-chip power-on reset
• On-chip RC oscillator
• Single 5 V operation
• Chip (SED1278D) and 80-pin QFP (SED1278F)
packages
(Compatible with HD 44780 and HD 66780 by Hitachi
Limited)
The SED1278 is equivalent to the HD 44780 and HD
66780 by Hitachi Limited. Before use, make sure that
there is no problem for practical use. It should be
noted that this is not intended to guarantee enforcement
of industrial property and other rights, or to grant
license for the use of this product.
EPSON
9–1
SED1278
SED1278
BLOCK DIAGRAM
OSC1
OSC2
Instruction Decoder
Cursor/ Printer Control
Instruction Register
DB 0
to
DB 7
I/O Buffer
Address
Counter ACC
Refresh Address Counter
7
Oscillation
Circuit
Daia Register
7
MPX
Timing Generator
XSCL
LP
FR
E
R/W
RS
V
SS
V
DC
V
1
V
2
V
3
V
4
V
5
I/O Control
Display Data RAM
DDRAM
80 Bytes
Shift Register 16 Bits
Common Driving
Output Circuit
MPX
8
COM 1 to
COM 16
SEG 1 to
SEG 40
Segment Driving
Output Circuit
Latch Circuit
MPX
5
Parallel/Serial
Data Converter
Shift Register
40 Bits
DO
40 Bits
Character Generator
RAM
(CGRAM)
64 Bits
5
Character Generator
RAM
(CGROM)
5 x 10 x 240 Bits
5
PACKAGE OUTLINE
64
41
65
40
80
25
1
24
9–2
EPSON
SED1278
24
25
1
80
SED1278D
40
41
64
65
PINOUT
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
Number
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin
Name
SEG2
SEG1
GND
OSC1
OSC2
V
1
V
2
V
3
V
4
V
5
LP
XSCL
V
DD
FR
DO
RS
R/W
E
DB0
DB1
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin
Name
DB2
DB3
DB4
DB5
DB6
DB7
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
Number
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin
Name
COM15
COM16
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
EPSON
9–3
SED1278
SED1278
PIN DESCRIPTION
MPU Interface
RS
Register select signal input. Selects
between the data and instruction registers
during CPU access.
RS = 0: Instruction register access cycle
RS = 1: Data register access cycle
This input selects between SED1278
register read and write cycles.
R/W = 0: Register write cycle
R/W = 1: Register read cycle
Read/write execute signal input.
DB0 to DB7
TTL level data input/output lines, for
connection to the system MPU data bus.
R/W
E
TABLE 1 The Function of the E Signal
RS
0
0
1
1
R/W
0
1
0
1
1
1
E
Operation
Instruction write cycle
Busy flag read cycle
Address counter read cycle
DDRAM or CGRAM data write cycle
DDRAM or CGRAM data read cycle
LCD Panel Interface
COM1 to COM16
Common driver outputs to the
LCD panel.
SEG1 to SEG40
Segment driver outputs to the LCD
panel.
OSC1
If the internal RC oscillator is used
to generate the LCD drive signals,
the feedback resistor, R
f
, is
connected to this pin. If an external
clock source is used, the clock is
connected to this pin.
OSC2
If the internal RC oscillator is used
to generate the LCD drive signals,
the feedback resistor, R
f
, is
connected to this pin. If an external
clock source is used, this pin is left
open.
External Segment Driver Interface
LP
XSCL
FR
DO
Data latch pulse output for an external
X-driver.
Data shift clock output for an external
X-driver.
LCD AC-drive waveform for an external
X-driver.
Display data output for an external X-driver.
9–4
EPSON
SED1278
TERMINAL CONFIGURATION
1.
Input terminal configuration (1)
V
DD
Applicable terminal
·E
· OSCI
Internal
V
SS
2.
Input terminal configuration (2)
With pull-up MOS resistor
V
DD
Applicable terminal
· RS, R/W
Internal
V
SS
3.
Output terminal configuration
V
DD
Internal
V
SS
EPSON
9–5
SED1278
Applicable terminal
· OSC2
· XSCL, LP, FR, DO
嵌入式系统
