®
SG2525A
SG3525A
REGULATING PULSE WIDTH MODULATORS
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8 TO 35 V OPERATION
5.1 V REFERENCE TRIMMED TO
±
1 %
100 Hz TO 500 KHz OSCILLATOR RANGE
SEPARATE OSCILLATOR SYNC TERMINAL
ADJUSTABLE DEADTIME CONTROL
INTERNAL SOFT-START
PULSE-BY-PULSE SHUTDOWN
INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
LATCHING PWM TO PREVENT MULTIPLE
PULSES
DUAL SOURCE/SINK OUTPUT DRIVERS
DIP16
16(Narrow)
DESCRIPTION
The SG3525A series of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to
±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between the C
T
and the discharge terminals
provide a wide range of dead time ad- justment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdown terminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltage lockout which keeps the out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludes approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525A output stage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS
(top view)
Type
SG2525A
SG3525A
Plastic DIP
SG2525AN
SG3525AN
SO16
SG2525AP
SG3525AP
June 2000
1/12
SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol
V
i
V
C
I
OSC
I
o
I
R
I
T
Supply Voltage
Collector Supply Voltage
Oscillator Charging Current
Output Current, Source or Sink
Reference Output Current
Current through C
T
Terminal
Logic Inputs
Analog Inputs
Total Power Dissipation at T
amb
= 70
°C
Junction Temperature Range
Storage Temperature Range
Operating Ambient Temperature :
SG2525A
SG3525A
Parameter
Value
40
40
5
500
50
5
– 0.3 to + 5.5
– 0.3 to V
i
1000
– 55 to 150
– 65 to 150
– 25 to 85
0 to 70
Unit
V
V
mA
mA
mA
mA
V
V
mW
°C
°C
°C
°C
P
tot
T
j
T
stg
T
op
THERMAL DATA
Symbol
R
th j-pins
R
th j-amb
R
th j-alumina
Parameter
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient
Thermal Resistance Junction-alumina (*)
Max
Max
Max
SO16
DIP16
50
80
50
Unit
°C/W
°C/W
°C/W
* Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15
×
20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
2/12
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
REFERENCE SECTION
V
REF
∆V
REF
∆V
REF
Output Voltage
Line Regulation
Load Regulation
T
j
= 25
°C
V
i
= 8 to 35 V
I
L
= 0 to 20 mA
Over Operating Range
Line, Load and
Temperature
V
REF
= 0 T
j
= 25
°C
10 Hz
≤f ≤
10 kHz,
T
j
= 25
°C
T
j
= 125
°C,
1000 hrs
T
j
= 25
°C
V
i
= 8 to 35 V
Over Operating Range
R
T
= 200 KΩ C
T
= 0.1
µF
R
T
= 2 KΩ C
T
= 470 pF
I
RT
= 2 mA
T
j
= 25
°C
Sync Voltage = 3.5 V
400
1.7
3
0.3
1.2
2
3.5
0.5
2
1
0.5
1
R
L
≥
10 MΩ
G
v
= 0 dB
T
j
= 25
°C
60
1
1.1
75
2
1.5
0.2
3.8
V
CM
= 1.5 to 5.2 V
V
i
= 8 to 35 V
60
50
5.6
75
60
0.5
3.8
60
50
1
2.8
2.5
5
10
1
60
1
1.1
75
2
1.5
0.2
5.6
75
60
0.5
2.2
5
80
40
20
±
2
±
0.3
±
3
5.05
5.1
10
20
20
5.15
20
50
50
5.2
100
200
50
±
6
±
1
±
6
120
400
1.7
3
0.3
1.2
2
3.5
0.5
2
1
2
1
1
2.8
2.5
10
10
1
2.2
4.95
80
40
20
±
2
±
1
±
3
5
5.1
10
20
20
5.2
20
50
50
5.25
100
200
50
±
6
±
2
±
6
120
V
mV
mV
mV
V
mA
µVrms
mV
%
%
%
Hz
KHz
mA
V
µs
V
mA
mV
µA
µA
dB
MHz
ms
V
V
dB
dB
SG2525A
Typ.
Max.
Min.
SG3525A
Typ.
Max.
Unit
∆V
REF
/∆T* Temp. Stability
*
Total Output Variation
Short Circuit Current
*
∆V
REF
*
*,
•
*,
•
∆f/∆T*
f
MIN
f
MAX
*,
•
*,
•
Output Noise Voltage
Long Term Stability
Initial Accuracy
Voltage Stability
Temperature Stability
Minimum Frequency
Maximum Frequency
Current Mirror
Clock Amplitude
Clock Width
Sync Threshold
Sync Input Current
V
OS
I
b
I
os
*
*,
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Gain Bandwidth
Product
DC Transconduct.
Output Low Level
Output High Level
CMR
PSR
Comm. Mode Reject.
Supply Voltage
Rejection
OSCILLATOR SECTION * *
ERROR AMPLIFIER SECTION (V
CM
= 5.1 V)
30 KΩ
≤
R
L
≤
1 MΩ
T
j
= 25
°C
3/12
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Conditions
Min.
PWM COMPARATOR
Minimum Duty-cycle
•
•
*
Maximum Duty-cycle
Input Threshold
Input Bias Current
Soft Start Current
Soft Start Low Level
Shutdown Threshold
V
SD
= 0 V, V
SS
= 0 V
V
SD
= 2.5 V
To outputs, V
SS
= 5.1 V
T
j
= 25
°C
V
SD
= 2.5 V T
j
= 25
°C
I
sink
= 20 mA
I
sink
= 100 mA
Output High Level
Under-Voltage Lockout
I
C
t
r
*
t
f
*
I
s
Collector Leakage
Rise Time
Fall Time
Supply Current
I
source
= 20 mA
I
source
= 100 mA
V
comp
and V
ss
= High
V
C
= 35 V
C
L
= 1 nF, T
j
= 25
°C
C
L
= 1 nF, T
j
= 25
°C
V
i
= 35 V
100
50
14
18
17
6
0.6
25
Zero Duty-cycle
Maximum Duty-cycle
SHUTDOWN SECTION
50
0.4
0.8
0.4
0.2
0.2
1
19
18
7
8
200
600
300
20
100
50
14
80
0.7
1
1
0.5
0.4
2
18
17
6
0.6
25
50
0.4
0.8
0.4
0.2
0.2
1
19
18
7
8
200
600
300
20
80
0.7
1
1
0.5
0.4
2
µA
V
V
mA
µs
V
V
V
V
V
µA
ns
ns
mA
45
0.7
49
0.9
3.3
0.05
3.6
1
0
45
0.7
49
0.9
3.3
0.05
3.6
1
0
%
%
V
V
µA
SG2525A
Typ.
Max.
Min.
SG3525A
Typ.
Max.
Unit
Shutdown Input Current V
SD
= 2.5 V
*
Shutdown Delay
Output Low Level
OUTPUT DRIVERS (each output) (V
C
= 20 V)
TOTAL STANDBY CURRENT
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
•
Tested at f
osc
= 40 KHz (R
T
= 3.6 KΩ, C
T
= 10nF, R
D
= 0
Ω).
Approximate oscillator frequency is defined by :
f=
1
C
T
(0.7 R
T
+ 3 R
D
)
.
DC transconductance (g
M
) relates to DC open-loop voltage gain (G
v
) according to the following equation : G
v
= g
M
R
L
where R
L
is the resistance
from pin 9 to ground. The minimum g
M
specification is used to calculate minimum G
v
when the error amplifier output is loaded.
4/12
SG2525A-SG3525A
TEST CIRCUIT
5/12
