SU572328FG8RWUU
May 17, 2006
Ordering Information
Part Numbers
SB572328FG8RWDB
Description
32Mx72 (256MB), DDR2, 244-pin Mini-DIMM, Registered,
ECC, 32Mx8 Based, DDR2-400-333, 30.00mm, Lead-Free
Module.
32Mx72 (256MB), DDR2, 244-pin Mini-DIMM, Registered,
ECC, 32Mx8 Based, DDR2-400-333, 30.00mm, Green
Module (RoHS Compliant).
32Mx72 (256MB), DDR2, 244-pin Mini-DIMM, Registered,
ECC, 32Mx8 Based, DDR2-533-444, 30.00mm.
32Mx72 (256MB), DDR2, 244-pin Mini-DIMM, Registered,
ECC, 32Mx8 Based, DDR2-533-444, 30.00mm, Lead-Free
Module.
32Mx72 (256MB), DDR2, 244-pin Mini-DIMM, Registered,
ECC, 32Mx8 Based, DDR2-533-444, 30.00mm, Green
Module (RoHS Compliant).
32Mx72 (256MB), DDR2, 244-pin Mini-DIMM, Registered,
ECC, 32Mx8 Based, DDR2-667-555, 30.00mm, Green
Module (RoHS Compliant).
Module Speed
PC2-3200 @ CL 3.0
SG572328FG8RWDB
PC2-3200 @ CL 3.0
SM572328FG8RWDG
SB572328FG8RWDG
PC2-4200 @ CL 4.0
PC2-4200 @ CL 4.0
SG572328FG8RWDG
PC2-4200 @ CL 4.0
SG572328FG8RWIL
PC2-5300 @ CL 5.0
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU572328FG8RWUU
May 17, 2006
Revision History
• May 17, 2006
Corrected the OCD Program in the EMRS on page 14.
Changed the Ambient Operating temperature to 0 to +65°C on page 16.
Added the Case Operating temperature on page 16.
• September 16, 2005
Corrected the DLL Enable in the EMRS on page 14.
• June 24, 2005
Added SG572328FG8RWIL to the Ordering Information on page 1.
Obsoleted SM572328FG8RWDB, SX572328FG8RWDB & SX572328FG8RWDG from the Ordering Information
on page 1 because the Module Process technologies are no longer supported.
• September 13, 2004
Added SX572328FG8RWDB, SG572328FG8RWDB, SX572328FG8RWDG & SG572328FG8RWDG to the
Ordering Information on page 1.
Corrected the Module Description on page 3 to show that the module is registered.
• July 30, 2004
Changed module speed from PC2-4300 to PC2-4200 in accordance with the new Jedec standard.
• June 15, 2004
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU572328FG8RWUU
May 17, 2006
256MByte (32Mx72) DDR2 SDRAM Module - 32Mx8 Based
244-pin Mini-DIMM, Registered, ECC
Features
• Standard
• Configuration
• Cycle Time
• CAS# Latency
:
:
:
:
JEDEC
ECC
5.0ns (DDR2-400)
3.75ns (DDR2-533)
3.0ns (DDR2-667)
3.0, 4.0 (DDR2-400/533)
4.0, 5.0 (DDR2-667)
0, 1.0, 2.0, 3.0 & 4.0
Read (CAS#) Latency - 1
4, 8
•
•
•
•
•
•
•
•
•
Burst Type
:
Sequential/Interleave
No. of Internal
Banks per SDRAM :
4
Operating Voltage :
1.8V
Refresh
:
8K/64ms
Device Physicals :
FBGA
Lead Finish
:
Gold
Length x Height
:
82.00mm x 30.00mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Vertical
:
Molex - 87782-2001
Horizontal
:
Molex - 87918-0001
• Posted CAS#/Additive
Latency (AL)
:
• Write Latency (WL)
:
• Burst Length
:
244-pin DDR2 Mini-DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
Pin Pin
No. Name
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
V
DDQ
CKE0
V
DD
BA2 (NC)
Pin Pin
No. Name
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
BA0
V
DD
WE#
V
DD
CAS#
V
DDQ
CS1# (NC)
ODT1 (NC)
V
DDQ
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
Pin Pin
No. Name
106 DQS6#
107 DQS6
108 V
SS
109 DQ50
110 DQ51
111 V
SS
112 DQ56
113 DQ57
114 V
SS
115 DQS7#
116 DQS7
117 V
SS
118 DQ58
119 DQ59
120 V
SS
121 SA0
122 SA1
123 V
SS
124 DQ4
125 DQ5
Pin Pin
No. Name
141 V
SS
142 DQ14
143 DQ15
144 V
SS
145 DQ20
146 DQ21
147 V
SS
148 DM2
149 NC
150 V
SS
151 DQ22
152 DQ23
153 V
SS
154 DQ28
155 DQ29
156 V
SS
157 DM3
158 NC
159 V
SS
160 DQ30
Pin Pin
No. Name
176 A15 (NC)
177 A14 (NC)
178 V
DDQ
179 A12
180 A9
181 V
DD
182 A8
183 A6
184 V
DDQ
185 A3
186 A1
187 V
DD
188 CK0
189 CK0#
190 V
DD
191 A0
192 BA1
193 V
DD
194 RAS#
195 V
DDQ
Pin Pin
No. Name
211 V
SS
212 DQ44
213 DQ45
214 V
SS
215 DM5
216 NC
217 V
SS
218 DQ46
219 DQ47
220 V
SS
221 DQ52
222 DQ53
223 V
SS
224 DU
225 DU
226 V
SS
227 DM6
228 NC
229 V
SS
230 DQ54
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU572328FG8RWUU
May 17, 2006
244-pin DDR2 Mini-DIMM Pin List (Contd.)
Pin Pin
No. Name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
Pin Pin
No. Name
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
NC
V
DDQ
A11
A7
V
DD
A5
A4
V
DDQ
A2
V
DD
V
SS
V
SS
NC
V
DD
A10/AP
Pin Pin
No. Name
91
92
93
94
95
96
97
98
99
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
Pin Pin
No. Name
126 V
SS
127 DM0
128 NC
129 V
SS
130 DQ6
131 DQ7
132 V
SS
133 DQ12
134 DQ13
135 V
SS
136 DM1
137 NC
138 V
SS
139 DU
140 DU
Pin Pin
No. Name
161 DQ31
162 V
SS
163 CB4
164 CB5
165 V
SS
166 DM8
167 NC
168 V
SS
169 CB6
170 CB7
171 V
SS
172 NC
173 V
DDQ
174 CKE1 (NC)
175 V
DD
Pin Pin
No. Name
196 CS0#
197 V
DDQ
198 ODT0
199 A13 (NC)
200 V
DD
201 NC
202 V
SS
203 DQ36
204 DQ37
205 V
SS
206 DM4
207 NC
208 V
SS
209 DQ38
210 DQ39
Pin Pin
No. Name
231 DQ55
232 V
SS
233 DQ60
234 DQ61
235 V
SS
236 DM7
237 NC
238 V
SS
239 DQ62
240 DQ63
241 V
SS
242 SDA
243 SCL
244 V
DDSPD
100 DQ48
101 DQ49
102 V
SS
103 SA2
104 NC
105 V
SS
Pin Description Table
Symbol
CK0
Type
SSTL_18
Polarity
Positive
Edge
Negative
Edge
Active High
Function
Positive line of the differential pair of system clock inputs. (All DDR2 SDRAM address and
control inputs are sampled on the rising edge of their associated clocks. Output data is refer-
enced at the crossings of the clocks.)
Negative line of the differential pair of system clock inputs.
On-Die Termination: ODT when high enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, and
DM. The ODT input will be ignored if disabled in Extended Mode Register (EMRS).
Activates the DDR2 SDRAM CLK signal when high and deactivates the CLK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated DDR2 SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored but previous operations
continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operations to be executed by the SDRAM.
Bank Address define to which bank an Activate, Read, Write or Precharge command is
being applied. Bank address also determines if the Mode Register or Extended Mode Regis-
ter is to be accessed during a MRS or EMRS cycle.
CK0#
ODT0
SSTL_18
SSTL_18
CKE0
SSTL_18
Active High
CS0#
SSTL_18
Active Low
RAS#, CAS#,
WE#
BA0~BA1
SSTL_18
SSTL_18
Active Low
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU572328FG8RWUU
May 17, 2006
Pin Description Table (Contd.)
Symbol
A0~A9,
A10/AP,
A11~A12
Type
SSTL_18
Polarity
-
Function
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10/AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state
of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. The
address inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins.
DDR2 SDRAM differential data strobe for input and output data.
DDR2 SDRAM differential data strobe for input and output data.
DM is an input mask signal for write data. Input data is masked when DM is sampled high
coincident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ/DQS loading.
Slave Address Select for EEPROM. These pins are used to configure the presence-detect
device.
Serial Bus Data Line for EEPROM. SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module. A resistor must be connected
from the SDA bus line to V
DD
to act as pull up on the system board.
Serial Bus Clock for EEPROM. SCL is used to synchronize the presence-detect data trans-
fer to and from the module. A resistor may be connected from the SCL bus line to V
DD
to act
as pull up on the system board.
Register and PLL control pin. When low, all register outputs will be driven low and the PLL
clocks to the DRAM and register will be set to low levels (the PLL will remain synchronized
with the input clock, if within spec range).
SDRAM positive power supply. 1.8V±0.1V
Power supply return (ground).
SDRAM I/O reference supply.
SDRAM I/O Driver positive power supply. 1.8V±0.1V
Serial EEPROM positive power supply (wired to a separate power pin at the connector which
supports operation from 1.7V to 3.6V.
No Connect.
Do not use.
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0#~DQS8#
DM0~DM8
SSTL_18
SSTL_18
SSTL_18
SSTL_18
-
Positive
Edge
Negative
Edge
Active High
SA0~SA2
SDA
LVTTL
LVTTL
-
-
SCL
LVTTL
-
RESET#
LV-CMOS
Active Low
V
DD
V
SS
V
REF
V
DDQ
V
DDSPD
NC
DU
Supply
Supply
Supply
Supply
Supply
-
-
-
-
-
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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