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SG572648FG8EZDG

DRAM

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厂商名称:SMART Modular Technology Inc

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器件参数
参数名称
属性值
厂商名称
SMART Modular Technology Inc
包装说明
,
Reach Compliance Code
unknown
Base Number Matches
1
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SG572648FG8EZUU
July 29, 2008
Ordering Information
Part Numbers
SG572648FG8EZDB
Description
64Mx72 (512MB), DDR2, 200-pin SO-RDIMM, Registered,
ECC, 64Mx8 Based, DDR2-400-333, 30.00mm, 22Ω DQ
termination, Green Module (RoHS-6 Compliant).
64Mx72 (512MB), DDR2, 200-pin SO-RDIMM, Registered,
ECC, 64Mx8 Based, DDR2-533-444, 30.00mm, 22Ω DQ
termination, Green Module (RoHS-6 Compliant).
64Mx72 (512MB), DDR2, 200-pin SO-RDIMM, Registered,
ECC, 64Mx8 Based, DDR2-667-555, 30.00mm, 22Ω DQ
termination, Green Module (RoHS-6 Compliant).
64Mx72 (512MB), DDR2, 200-pin SO-RDIMM, Registered,
ECC, 64Mx8 Based, DDR2-800-555, 30.00mm, 22Ω DQ
termination, Green Module (RoHS-6 Compliant).
64Mx72 (512MB), DDR2, 200-pin SO-RDIMM, Registered,
ECC, 64Mx8 Based, DDR2-800-666, 30.00mm, 22Ω DQ
termination, Green Module (RoHS-6 Compliant).
Module Speed
PC2-3200 @ CL 3.0
SG572648FG8EZDG
PC2-4200 @ CL 4.0
SG572648FG8EZIL
PC2-5300 @ CL 5.0
SG572648FG8EZIR
PC2-6400 @ CL 5.0
SG572648FG8EZKF
PC2-6400 @ CL 6.0
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SG572648FG8EZUU
July 29, 2008
Revision History
• July 29, 2008
Corrected the notches in the Phsical Dimensions on page 9.
• April 7, 2008
Added SG572648FG8EZIR & SG572648FG8EZKF to the Ordering Information on page 1.
• March 21, 2007
Corrected the input capacitance on page 17.
• July 18, 2006
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SG572648FG8EZUU
July 29, 2008
512MByte (64Mx72) DDR2 SDRAM Module - 64Mx8 Based
200-pin SO-RDIMM, Registered, ECC
Features
• Standard
• Configuration
• Cycle Time
:
:
:
JEDEC
ECC
5.0ns (DDR2-400)
3.75ns (DDR2-533)
3.0ns (DDR2-667)
2.5 (DDR2-800)
3.0, 4.0 (-DB/-DG)
4.0, 5.0 (-IL/-IR)
5.0, 6.0 (-KF)
0, 1.0, 2.0, 3.0 & 4.0
Read (CAS#) Latency - 1
4, 8
Burst Type
:
Sequential/Interleave
Module Ranks
:
1 Rank of x8 devices
No. of Devices
:
9
No. of Internal
Banks per SDRAM :
4
Operating Voltage :
1.8V
Refresh
:
8K/64ms
Device Physicals :
FBGA
Lead Finish
:
Gold
Length x Height
:
67.60mm x 30.00mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Horizontal
:
AMP - 1473150-4
• CAS# Latency
:
• Posted CAS#/Additive
Latency (AL)
:
• Write Latency (WL)
:
• Burst Length
:
DDR2 200-pin SO-RDIMM Pin List
Pin Pin
No. Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
V
REF
DQ0
V
SS
DQ1
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
Pin Pin
No. Name
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
Pin Pin
No. Name
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CKE0
Pin Pin
No. Name
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
V
SS
DQ28
DQ29
V
SS
DM3
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
V
SS
CB6
CB7
V
SS
CB2
CB3
V
SS
Pin Pin
No. Name
101 V
DD
103 A5
105 A3
107 A2
109 V
DD
111 A10/AP
113 BA0
115 RAS#
117 V
DD
119 CAS#
Pin Pin
No. Name
102 A6
104 A4
106 V
DD
108 A1
110 A0
112 BA1
114 V
DD
116 WE#
118 CS0#
120 ODT0
Pin Pin
No. Name
151 V
SS
153 DQS5#
155 DQS5
157 V
SS
159 DQ42
161 DQ43
163 V
SS
165 DQ48
167 DQ49
169 V
SS
171 DQS6#
173 DQS6
175 V
SS
177 DQ50
179 DQ51
181 V
SS
183 DQ56
185 DQ57
187 V
SS
189 DQS7#
Pin Pin
No. Name
152 V
SS
154 DM5
156 V
SS
158 DQ46
160 DQ47
162 V
SS
164 DQ52
166 DQ53
168 V
SS
170 DM6
172 V
SS
174 DQ54
176 DQ55
178 V
SS
180 DQ60
182 DQ61
184 V
SS
186 DM7
188 DQ62
190 V
SS
121 CS1# (NC) 122 A13
123 V
DD
124 V
DD
125 ODT1 (NC) 126 CK0
127 CS3# (NC) 128 CK0#
129 DQ32
131 V
SS
133 DQ33
135 DQS4#
137 DQS4
139 V
SS
130 V
SS
132 DQ36
134 DQ37
136 V
SS
138 DM4
140 V
SS
CKE1 (NC) 90
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SG572648FG8EZUU
July 29, 2008
DDR2 200-pin SO-RDIMM Pin List (Contd.)
Pin Pin
No. Name
41
43
45
47
49
DQ17
V
SS
DQS2#
DQS2
V
SS
Pin Pin
No. Name
42
44
46
48
50
RESET#
DM2
V
SS
DQ22
DQ23
Pin Pin
No. Name
91
93
95
97
99
Pin Pin
No. Name
BA2 (NC)
A14 (NC)
A11
V
DD
Pin Pin
No. Name
141 DQ34
143 DQ35
145 V
SS
147 DQ40
149 DQ41
Pin Pin
No. Name
142 DQ38
144 DQ39
146 V
SS
148 DQ44
150 DQ45
Pin Pin
No. Name
191 DQS7
193 DQ58
195 V
SS
197 DQ59
199 V
DDSPD
Pin Pin
No. Name
192 DQ63
194 SDA
196 SCL
198 SA1
200 SA0
CS2# (NC) 92
V
DD
A12
A9
A7
94
96
98
100 A8
Pin Description Table
Symbol
CK0
Type
SSTL_18
Polarity
Positive Edge
Function
Positive line of the differential pair of system clock inputs. (All DDR2 SDRAM address and
control inputs are sampled on the rising edge of their associated clocks. Output data is ref-
erenced at the crossings of the clocks.)
Negative line of the differential pair of system clock inputs.
On-Die Termination: ODT when high enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, and
DM. The ODT input will be ignored if disabled in Extended Mode Register (EMRS).
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored but previous operations con-
tinue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operations to be executed by the SDRAM.
Bank Address define to which bank an Activate, Read, Write or Precharge command is
being applied. Bank address also determines if the Mode Register or Extended Mode
Register is to be accessed during a MRS or EMRS cycle.
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10/AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless of
the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge. The address inputs also provide the op-code during Mode Register Set com-
mands.
CK0#
ODT0
SSTL_18
SSTL_18
Negative Edge
Active High
CKE0
SSTL_18
Active High
CS0#
SSTL_18
Active Low
RAS#, CAS#,
WE#
BA0~BA1
SSTL_18
SSTL_18
Active Low
-
A0~A9, A10/AP,
A11~A13
SSTL_18
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SG572648FG8EZUU
July 29, 2008
Pin Description Table (Contd.)
Symbol
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0#~DQS8#
DM0~DM8
Type
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Polarity
-
Positive Edge
Negative Edge
Active High
Function
Data and Check Bit Input/Output pins.
SDRAM differential data strobe for input and output data.
SDRAM differential data strobe for input and output data.
DM is an input mask signal for write data. Input data is masked when DM is sampled high
coincident with that input data during a write access. DM is sampled on both edges of
DQS. Although DM pins are input only, the DM loading matches the DQ/DQS loading.
Slave Address Select for EEPROM. These pins are used to configure the presence-detect
device.
Serial Bus Data Line for EEPROM. SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module. A resistor must be
connected from the SDA bus line to V
DDSPD
to act as pull up on the system board.
Serial Bus Clock for EEPROM. SCL is used to synchronize the presence-detect data
transfer to and from the module. A resistor may be connected from the SCL bus line to
V
DDSPD
to act as pull up on the system board.
Register and PLL control pin. When low, all register outputs will be driven low and the PLL
clocks to the DRAM and register will be set to low levels (the PLL will remain synchronized
with the input clock, if within spec range).
SDRAM positive power supply. 1.8V±0.1V
Power supply return (ground).
SDRAM I/O reference supply.
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports operation from 1.7V to 3.6V).
No Connect.
SA0~SA1
SDA
LVTTL
LVTTL
-
-
SCL
LVTTL
-
RESET#
LV-CMOS
Active Low
V
DD
V
SS
V
REF
V
DDSPD
NC
Supply
Supply
Supply
Supply
-
-
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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参数对比
与SG572648FG8EZDG相近的元器件有:SG572648FG8EZKF、SG572648FG8EZDB。描述及对比如下:
型号 SG572648FG8EZDG SG572648FG8EZKF SG572648FG8EZDB
描述 DRAM DRAM DRAM
厂商名称 SMART Modular Technology Inc SMART Modular Technology Inc SMART Modular Technology Inc
Reach Compliance Code unknown unknown unknown
Base Number Matches 1 1 1
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