Si52146
P C I - E
X P R E S S
G
E N
1 , G
E N
2, G
E N
3 , & G
EN
4 S
IX
O
U T P U T
C
LOCK
G
ENERATOR
Features
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Gen 3 SRNS Compliant
Supports Serial-ATA (SATA) at
100 MHz
Low power push-pull HCSL
compatible differential outputs
No termination resistors required
Dedicated output enable pins for
each clock
Pin selectable spread control
Up to six PCI-Express clock outputs
25 MHz crystal input or clock input
I
2
C support with readback
capabilities
Triangular spread spectrum profile
for maximum electromagnetic
interference (EMI) reduction
Industrial temperature:
–40 to 85 °C
3.3 V Power supply
32-pin QFN package
Ordering Information:
See page 18
Applications
Network attached storage
Multi-function printer
Wireless access point
Switches
Pin Assignments
VDD_CORE
CKPWRGD/PDB
1
OE_DIFF1
1
OE_DIFF0
1
Description
The Si52146 is a high-performance, PCIe clock generator that can source six
PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are
compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common
clock specifications. The device has six output enable control pins for
enabling and disabling differential outputs. A spread spectrum control pin for
EMI reduction is also available. The small footprint and low power
consumption makes the Si52146 the ideal clock solution for consumer and
embedded applications. Measuring PCIe clock jitter is quick and easy with the
Silicon Labs PCIe Clock Jitter Tool. Download it for free at
www.silabs.com/
pcie-learningcenter.
XIN/CLKIN
SDATA
26
32
VDD_DIFF
OE_DIFF2
1
SSON
2
OE_DIFF3
1
OE_DIFF4
1
OE_DIFF5
1
31
30
XOUT
29
28
27
25
24 VDD_DIFF
23 DIFF5
22 DIFF5
21 VDD_DIFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
GND
SCLK
20
DIFF4
19 DIFF4
18
DIFF3
NC
VDD_DIFF
17 DIFF3
DIFF1
DIFF1
Functional Block Diagram
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
DIFF0
XIN/CLKIN
XOUT
DIFF1
PLL1
(SSC)
Divider
DIFF2
DIFF3
DIFF4
DIFF5
SCLK
SDATA
CKPWRGD/PDB
Control
RAM
Control & Memory
OE [5:0]
SSON
Rev. 1.4 4/16
Copyright © 2016 by Silicon Laboratories
VDD_DIFF
VDD_DIFF
DIFF2
DIFF0
DIFF0
DIFF2
Si52146
Si52146
2
Rev. 1.4
Si52146
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. CKPWRGD/PDB (Power Down) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. PDB (Power Down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. OE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.8. SSON Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.4
3
Si52146
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Power Down Current
Dynamic Supply Current
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
I
OZ
C
IN
C
OUT
L
IN
I
DD
_
PD
I
DD_3.3V
All outputs enabled. Differ-
ential clocks with 5” traces
and 2 pF load.
Test Condition
3.3 ±5%
Control input pins
Control input pins
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up
resistors, 0 < V
IN
< V
DD
Min
3.135
2.0
V
SS
– 0.3
2.2
—
—
–5
–10
1.5
—
—
—
—
Typ
3.3
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
10
5
6
7
1
60
Unit
V
V
V
V
V
A
A
A
pF
pF
nH
mA
mA
4
Rev. 1.4
Si52146
Table 2. AC Electrical Specifications
Parameter
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
Duty Cycle
Symbol
L
ACC
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
T
DC
T
SKEW
T
CCJ
Pk-Pk
RMS
GEN2
RMS
GEN2
RMS
GEN3
RMS
GEN3_SRNS
Test Condition
Measured at V
DD
/2 differential
Measured at V
DD
/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
Measured at 0 V differential
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
Measured at 0 V differential
Measured differentially from
±150 mV
Min
—
47
0.5
—
—
2
—
—
–35
45
—
—
0
0
0
0
—
Typ
—
—
—
—
—
—
—
—
—
—
—
35
30
1.75
1.75
0.5
0.35
Max
250
53
4.0
250
350
VDD+0.3
0.8
35
—
55
800
50
50
2.1
2.0
0.6
0.42
Unit
ppm
%
V/ns
ps
ps
V
V
uA
uA
%
ps
ps
ps
ps
ps
ps
ps
Output-to-Output skew
DIFF Cycle to Cycle Jitter
PCIe Gen 1 Pk-Pk,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Separate Reference No
Spread, SRNS
PCIe Gen 4 Phase Jitter,
Common Clock
Long Term Accuracy
Rising/Falling Slew Rate
Voltage High
Voltage Low
Crossing Point Voltage at
0.7 V Swing
Spread Range
RMS
GEN4
L
ACC
T
R
/T
F
V
HIGH
V
LOW
V
OX
SPR-2
—
—
1
—
–0.3
300
0.5
—
—
—
—
—
–0.5
0.6
100
8
1.15
—
550
—
ps
ppm
V/ns
V
V
mV
%
Down spread
—
Notes:
1.
Visit
www.pcisig.com
for complete PCIe specifications.
2.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3.
Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
Rev. 1.4
5
