Si5364-EVB
E
V A L U A T I O N
B
O A R D F O R
Si 5 36 4 S O N E T / S D H P
R E C I S I O N
P
ORT
C
ARD
C
LOCK
IC
Description
The Si5364-EVB is the evaluation board for the Si5364
SONET/SDH Precision Port Card Clock IC. This
evaluation board provides access to all signals
associated with normal operation of the device. This
circuit board also is designed to provide access to signals
that are reserved for factory testing purposes.
Features
Si5364 device can be powered directly from either a
3.3 or 2.5 V supply
Differential I/Os ac-coupled on board
Differential inputs terminated on board
Control input signals are switch/jumper configurable
Status outputs brought out to headers for access
LED status indicators reflect state of status outputs
LED status indicators can be disabled for device
power measurements
Function Block Diagram
3.3 V or 2.5 V
S upply
Power
S upply
Input
2.5 V L DO
R egula tor
Control
Input
J um per
Header
Status
O utput
Signal
Header
LED
D riv ers
LED
Status
Indicators
3.3 V/2.5 V
Supply
Selection
t
e
x
t
CLKO UT_1
t
e
x
t
C LKIN_A
Control
Inputs
Status
Outputs
+
50
Ω
50
Ω
C LKO UT_1
–
t
e
x
t
+
CLKO UT_2
C LKIN_A
+
50
Ω
50
Ω
–
C LKO UT_2
–
+
t
e
x
t
C LKIN_B
–
C LKIN_B
Si5364
+
50
Ω
50
Ω
C LKO UT_3
+
–
R EF/CLK IN_F
–
+
t
e
x
t
CLKO UT_3
50
Ω
50
Ω
C LKO UT_4
–
t
e
x
t
RE F/CLK IN _F
t
e
x
t
Factory
Test
Input
Header
Factory
Tes t
O utput
Header
Factory
Test
Serial
Input
Factory
Test
Serial
O utput
Fac tory
Test
Analog
Output
CLKO UT_4
t
e
x
t
Preliminary Rev. 0.33 6/02
Copyright © 2002 by Silicon Laboratories
Si5364-EVB-033
Si 5364- EV B
Functional Description
The Si5364-EVB is the evaluation board for the Si5364
SONET/SDH Precision Port Card Clock IC. This
evaluation board provides access to all signals
associated with normal operation of the device. This
circuit board also is designed to provide access to signals
that are reserved for factory testing purposes.
DECDELAY. They are routed to push button switches
SW1 and SW2, respectively, through headers JP4 and
JP5. Inverters U6 and U7 condition the action of these
switches before being sent to the Si5364 device.
Pressing and releasing these switches provides a single
pulse to the control input for the Si5364. This is a
convenient method for evaluating the operation of the
INCDELAY and DECDELAY functions. Resistors R26
and R27 allow the user to disconnect the switches from
the device and drive the inputs from another source. JP4
and JP5 are not populated when shipped from the
factory. If an external source is required to drive the
INCDELAY and DECDELAY inputs, then populate these
two headers. This provides the user a convenient location
to connect the source.
Each LVTTL input on the Si5364 device has an internal
pull-down mechanism. The control inputs default to a low
state if no device drives the input.
Power Supply Selection and Connections
The Si5364-EVB board is switch selectable for
operation using either a single 3.3 V or a single 2.5 V
supply.
For operation using a 3.3 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board’s power connector, J15.
2. Remove the connection between VDD33 and VDD25 by
removing the jumper on header JPI.
3. Set VSEL33 high by sliding the switch on the VSEL33
(JP3) to the side marked “1”.
4. Connect the power supply ground lead and 3.3 V supply
lead to the GND and VDD terminals of the board’s power
connector, J15.
RSTN/CAL Settings for Normal Operation
and Self-Calibration
The RSTN/CAL signal is an LVTTL input to the Si5364
and has an on-chip pull down mechanism. This pin must
be set high to enable normal operation of the Si5364
device.
Setting RSTN/CAL low forces the Si5364 into a reset
state. A low-to-high transition of RSTN/CAL enables the
part and initiates a self-calibration sequence.
The Si5364 device automatically initiates a self-
calibration at power-up if the RSTN/CAL signal is held
high. A self-calibration of the device also can be manually
initiated by pushing the RSTN/CAL switch, SW3, then
releasing. Self-calibration must be initiated manually after
changing the state of either the BWSEL[1:0] control
inputs or the FEC[1:0] inputs.
Whether manually initiated or automatically initiated at
power-up, the self-calibration process requires the
presence of a valid input clock. If the self-calibration is
initiated without a valid clock present, the device waits for
a valid clock before completing the self-calibration. The
Si5364 clock outputs drift to the lower end of the
operating frequency range as the device waits for a valid
clock. After the input clock is validated, the calibration
process runs to completion, the device locks to the input,
and the clock outputs shifts to their target frequencies.
Subsequent losses of the input clock do not require re-
calibration. If the clock input is lost after self-calibration,
the device enters Digital Hold mode. When the input
clock returns, the device re-locks to the input clock
without performing a self-calibration.
For operation using a 2.5 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board’s power connector, J15.
2. Set VSEL33 low by sliding the switch on the VSEL33 (JP3)
to the side marked “0”.
3. Connect VDD33 and VDD25 by installing a jumper
between one of the 3.3 V pins and one of the 2.5 V pins on
header JPI.
4. Connect the power supply ground lead and 2.5 V supply
lead to the GND and VDD terminals of the board’s power
connector, J15.
Power Consumption
Typical supply current draw for the Si5364-EVB with LED
indicators disabled and one clock output enabled is
120 mA. Each additional clock output that is enabled
adds approximately 15 mA. LED indicators, when
enabled, adds approximately 8 mA for each indicator that
is illuminated.
Si5364 Control Inputs
Most of the control inputs to the Si5364 are routed to the
center post of a SPDT switch located at JP1. The
switches are wired with the signal on the center pin,
VDD33 on one side pin, and GND on the other side pin.
Each input is easily configurable to a high or a low state.
There are three inputs to the Si5364 that are not routed to
switches at JP1. Two of these signals are INCDELAY and
2
Preliminary Rev. 0.33
Si5364-EVB
Status Signals
The status outputs from the Si5364 device are each
routed to one pin of a two-row header, JP11. The header
is wired so that the signals are present on one side of the
header and a ground reference is present on the other.
The letter S marks the row of signal pins and the row of
ground pins is marked with the letter G.
On the Si5364-EVB board, the status outputs are also
routed to two buffer/driver ICs (U4 and U5) that drive one
LED indicator for each status signal.
tantalum capacitor. This is the suggested compensation
circuit for Si5364 devices.
There are two considerations for selecting this
combination of compensation resistor and capacitor.
First, is the stability of the regulator. The second is noise
filtering.
The acceptable range for the time constant at this node
is 15
µs
to 50
µs.
The capacitor used on the board is a
33
µF
capacitor with an ESR of .8
Ω.
This yields a time
constant of 26.4
µs.
The designer could decide to use a
330
µF
capacitor with an ESR of .15
Ω.
This yields a
time constant of 49.5
µs.
Each of these cases provide a
compensation circuit that makes the output of the
regulator stable.
The second issue is noise filtering. For this, more
capacitance is usually better. For the two cases
described above, the 330
µF
case provides greater
noise filtering. However, the large case size of the
330
µF
capacitor might make it impractical for many
applications. The Si5364 device is specified with the
33
µF
cap.
Enabling and Disabling the Status Indicator
LEDs
The status LED driver outputs can be disabled. The
disabled driver outputs are placed into a high impedance
state to get a more accurate measurement of the current/
power being consumed by the Si5364 device. The LED
drivers are enabled when the switch at JP9 is switched to
ON. The driver outputs are disabled when the switch is
set to OFF.
Factory Test Headers
Locations for headers JP8 and JP10 are included on the
SI5364-EVB for factory testing. For customer evaluation,
these locations are not populated.
Default Jumper Settings
The default jumper settings for the Si5364-EVB board are
given in Table 1 on page 4. These settings configure the
board for operation from a 3.3 V supply.
Differential Clock Input Signals
The differential clock inputs to the Si5364-EVB are
terminated on the board at a location near the input SMA
connectors. The input SMA connectors are ac coupled to
the termination circuit. The termination circuit consists of
two 50
Ω
resistors and a 0.1
µF
capacitor, connected so
that the positive and negative inputs of the differential pair
each see a 50
Ω
termination to "ac ground", and the line-
to-line termination impedance is 100
Ω.
The signals are
then routed to the Si5364 device.
Single-ended operation is accomplished by supplying a
signal to one of the differential inputs, typically the
positive input. The other input should be shorted to
ground with an SMA shorting plug.
Differential Clock Output Signals
The differential clock outputs from the Si5364 device are
routed to the perimeter of the circuit board using 50
Ω
transmission structures. The capacitors that provide ac-
coupling are located near the clock output SMA
connectors.
Internal Regulator Compensation
The Si5364-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0
Ω
resistor. The
capacitor pads are populated with a low ESR 33
µF
Preliminary Rev. 0.33
3
Si 5364- EV B
Table 1. Si5364-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location
JP3
JP12
JP1
Signal
VSEL33
VDD33
VALTIME
SMC/S3N
DSBLFOS
RVRT
AUTOSEL
DSBLFSYNC
MANCNTRL[0]
MANCNTRL[1]
FEC[0]
FEC[1]
BWSEL[0]
BWSEL[1]
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
FXD_DELAY
JP9
JP2
JP15
LED ENABLE_N
SYNCIN
FSYNC
State
1
Open
0
1
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
0
ON
No Jumper
Installed
No Jumper
Installed
Notes
Si5364 device Internal Regulator enabled
Si5364 device VDD33 pins not connected to 2.5 V supply
plane
100 ms Validation Time
SONET Minimum Clock criteria selected
Frequency Offset alarms enabled
Revertive clock switching mode selected
Automatic input Selection enabled
FSYNC output enabled
CLKIN_A would be selected if AUTOSEL = 0
CLKIN_A would be selected if AUTOSEL = 0
FEC scaling factor = 1/1 (no FEC scaling)
FEC scaling factor = 1/1 (no FEC scaling)
Loop Bandwidth = 6400 Hz
Loop Bandwidth = 6400 Hz
CLKOUT_1 = 622 MHz Range
CLKOUT_1 = 622 MHz Range
CLKOUT_2 = 622 MHz Range
CLKOUT_2 = 622 MHz Range
CLKOUT_3 = 622 MHz Range
CLKOUT_3 = 622 MHz Range
CLKOUT_4 = 622 MHz Range
CLKOUT_4 = 622 MHz Range
Fixed Delay mode disabled
LED Status Indicators enabled
Header for SYNCIN input signal
Header for FSYNC output signal
4
Preliminary Rev. 0.33
3.3V
3.3V
3.3V
74LCX244
20
VCC
D1
D2
D3
D4
D5
R6
R7
R8
R5
R4
1OE
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
10
GND
U4
74LCX244
20
VCC
1OE
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
1
D6
D7
D8
2A1
2A2
2A3
2A4
10
GND
U5
JP9
1
3
1
3
2
2
1x3 HEADER
C3
0.1uf, 0603
C4
0.1uf, 0603
2Y1
2Y2
2Y3
2Y4
2OE
9
7
5
3
19
D9
D10
R9
R10
R11
R12
R13
120, 0603
120, 0603
120, 0603
120, 0603
1k, 0603
3.3V
2OE
19
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
1
1k, 0603
1k, 0603
1k, 0603
1k, 0603
1k, 0603
2.5V
JP1
2
VALTIME
E4
E5
E6
F4
F5
F6
5
SMC/S3N
8
DSBLFOS
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
RVRT
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
11
E7
E8
E9
F7
F8
F9
G4
G5
G6
G7
G8
H8
J8
K8
2
4
6
8
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
18
16
14
12
14
AUTOSEL
17
DSBLFSYNC
CLKIN_A+
CLKIN_A-
CLKIN_B+
CLKIN_B-
REF/CLKIN_F+
REF/CLKIN_F-
CLKIN_A+
CLKIN_A-
CLKIN_B+
CLKIN_B-
REF/CLKIN_F+
REF/CLKIN_F-
CLKOUT_1+
CLKOUT_1-
CLKOUT_2+
CLKOUT_2-
CLKOUT_3+
CLKOUT_3-
CLKOUT_4+
CLKOUT_4-
11
13
15
17
9
7
5
3
C2
C1
G1
G2
E2
E1
CLKOUT_1+
CLKOUT_1-
CLKOUT_2+
CLKOUT_2-
CLKOUT_3+
CLKOUT_3-
CLKOUT_4+
CLKOUT_4-
20
K4
K3
K6
K7
K10
K9
H10
G10
MANCNTRL[0]
23
U1
Si5364_revB
MANCNTRL[1]
26
FEC[0]
29
FEC[1]
32
BWSEL[0]
35
BWSEL[1]
38
FRQSEL_1[0]
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
FSYNC
2
4
6
8
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
18
16
14
12
F10
E10
D10
A5
A6
A7
A8
A9
A10
B10
J1
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
FSYNC
41
FRQSEL_1[1]
44
FRQSEL_2[0]
RES/DEV_ID[0]
RES/DEV_ID[1]
RES/DEV_ID[2]
RES/ANAOUT
11
13
15
17
B8
B7
B6
C6
RES/DEV_ID[0]
RES-DEV)ID[1]
REV/DEV_ID[2]
RES/ANAOUT
47
FRQSEL_2[1]
50
FRQSEL_3[0]
53
FRQSEL_3[1]
56
REXT
FRQSEL_4[0]
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
BWSEL[0]
BWSEL[1]
FEC[0]
FEC[1]
MANCNTRL[0]
MANCNTRL[1]
DSBLFSYNC
AUTOSEL
RVRT
RSTN/CAL
VALTIME
SMC/S3N
DSBLFOS
FXDDELAY
SYNCIN
INCDELAY
DECDELAY
VSEL33
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
BWSEL[0]
BWSEL[1]
FEC[0]
FEC[1]
MANCNTRL[0]
MANCNTRL[1]
DSBLFSYNC
AUTOSEL
RVRT
RSTN/CAL
VALTIME
SMC/S3N
DSBLFOS
FXDDELAY
SYNCIN
INCDELAY
DECDELAY
VSEL33
RES/TMODE[0]
RES/TMODE[1]
RES/TMODE[2]
RES/REFIN[0]
RES/REFIN[1]
RES/REFIN[2]
RES/PFDTEST
C9
C8
C7
D2
F1
F2
D1
RES/TMODE[0]
RES/TMODE[1]
RES/TMODE[2]
RES/REFIN[0]
RES/REFIN[1]
RES/REFIN[2]
RES/PFDTEST
J3
J4
J6
J7
J10
J9
G9
H9
A2
B2
A3
B3
A4
B4
H2
B1
C10
K2
J2
B9
B5
C5
H1
C3
C4
D3
FRQSEL_4[1]
1
3
4
6
7
9
10
12
13
15
16
18
19
21
22
24
25
27
28
30
31
33
34
36
37
39
40
42
43
45
46
48
49
51
52
54
55
57
58
60
61
63
R1
10k, 0603
3.3V
R29
0, 0402
1
3
SW3
101-0161
2
JP6
JP11
2
1
3
RSTN/CAL
3.3V
JP8
2
5
8
11
14
17
20
20
RES/PFDTEST
17
RES/REFIN[2]
14
RES/REFIN[1]
11
RES/REFIN[0]
8
RES/TMODE[2]
5
RES/TMODE[1]
4.99k, 0603
2
RES/TMODE[0]
1
3
5
7
2
4
6
8
RES/DEV_ID[0]
RES-DEV)ID[1]
REV/DEV_ID[2]
RES/ANAOUT
JP10
R28
JP2
1
3
1
3
2
2
SYNCIN
1x3 HEADER
JP3
1
3
1
3
2
2
VSEL33
Preliminary Rev. 0.33
1
3
4
6
7
9
10
12
13
15
16
18
19
21
1
3
4
6
7
9
10
12
13
15
16
18
19
21
7x3 HEADER
1x3 HEADER
For engineering test purposes only. Not
needed for customer application.
D4
D5
D6
D7
D8
D9
E3
F3
G3
H3
H4
H5
H6
H7
J5
K5
1
3
5
7
2
4
6
8
62
FXDDELAY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
59
K1
3.3V
3.3V
R26
0, 0402
1
3
1
3
JP4
101-0161
0.1uf, 0603
3
SW2
C2
2
INCDELAY
74SZ14
2
2
4
R3
100k, 0402
U7
5
1
3
R27
LOS_A
LOS_B
LOS_F
FOS_A
FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV
CAL_ACTV
20
18
16
14
12
10
8
6
4
2
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
19
17
15
13
11
9
7
5
3
1
FSYNC
0, 0402
1
3
JP5
2
2
DECDELAY
1
2
JP15
R2
100k, 0402
U6
5
2
4
SW1
C1
3
74SZ14
101-0161
0.1uf, 0603
Si5364-EVB
Figure 1. Si5364-EVB Typical Application Schematic (page 1 of 2)
5
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