Si5381/82 Data Sheet
Multi-DSPLL Wireless Jitter Attenuating Clocks
KEY FEATURES
The Si5381/82 is a wireless multi-PLL, jitter-attenuating clock that leverages Silicon
Labs’ latest fourth-generation DSPLL technology to address the form factor, power, and
performance requirements demanded by radio area network equipment, such as small
cells, baseband units, and distributed antenna systems (DAS). The Si538x is the indus-
try’s first multi-PLL wireless clock generator family capable of replacing discrete, high-
performance, VCXO-based clocks with a fully integrated CMOS IC solution. The
Si5381/82 features a multi-PLL architecture that supports independent timing paths for
JESD wireless clocks with less than 85 fs typical phase jitter as well as Ethernet and oth-
er low-jitter, general-purpose clocks. DSPLL technology also supports free-run and hold-
over operation as well as automatic and hitless input clock switching. This unparalleled
integration reduces power and size without compromising the stringent performance and
reliability demanded in wireless applications.
Applications
• Pico cells, small cells
• Mobile backhaul
• Multiservice Distributed Access Systems (MDAS)
• Supports simultaneous wireless and
general-purpose clocking in a single
device
• Jitter performance: 85 fs RMS typ (12
kHz–20 MHz)
• Input frequency range:
• Differential: 8 kHz – 750 MHz
• LVCMOS: 8 kHz – 250 MHz
• Output frequency range:
• JESD204B: 480 kHz - 2.94912 GHz
• Differential: 1 Hz – 712.5 MHz
• LVCMOS: 480 kHz – 250 MHz
Si5381/82
Integrated XO Circuit
OSC
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
I C/SPI
÷INT
Control/
Status
÷INT
OUT9
OUT9A
2
OUT0A
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
IN0
÷INT
DSPLL
C
DSPLL
D
DSPLL
A
DSPLL
B
Si5381
IN1
÷INT
IN2
÷INT
IN3
÷INT
Si5382
NVM
silabs.com
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.9
Si5381/82 Data Sheet
Feature List
1. Feature List
The Si5381/82 highlighted features are listed below.
• Digital frequency synthesis eliminates external VCXO and an-
alog loop filter components
• DSPLL_B supports high-frequency, wireless clocking. Re-
maining three DSPLLs support general-purposing clocking
• Integrated crystal option (Grade E)
• Input frequency range:
• Differential: 7.68 MHz–750 MHz
• LVCMOS: 10 MHz–250 MHz
• Output frequency range (DSPLL_B):
• Differential: up to 2.94912 GHz
• LVCMOS: up to 250 MHz
• Output frequency range (DSPLL_A/C/D):
• Differential: up to 735 MHz
• LVCMOS: up to 250 MHz
• Excellent jitter performance:
• DSPLL_B: 85 fs typ (12 kHz - 20 MHz)
• DSPLL_A/C/D: 150 fs typ (12 kHz - 20 MHz)
• Phase noise floor: –165 dBc/Hz
• Spur performance: –95 dBc max (relative to a 122.88 MHz
carrier)
• Flexible crosspoints route any input to any output clock
• Configurable outputs:
• Compatible with LVDS, LVPECL, LVCMOS, CML, HCSL
• Programmable signal amplitude
• Adjustable output-output delay: 68 ps/step, ±128 steps
• Independent output supply pins: 3.3, 2.5, or 1.8 V
• Core voltage:
• VDD = 1.8 V ±5%
• VDDA = 3.3 V ±5%
• Automatic free-run, lock, and holdover modes
• Digitally selectable loop bandwidth: DSPLL_B: 1 Hz to 4 kHz
• Hitless switching between input clocks
• Status monitoring (LOS, OOF, LOL)
• Serial interface: I
2
C or SPI in-circuit programmable with non-
volatile OTP memory
• ClockBuilder
TM
Pro software tool simplifies device configura-
tion
• 4 input, 12 output, 64QFN
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Preliminary Rev. 0.9 | 2
Si5381/82 Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide
Maximum Output Frequency
4G/LTE
JESD204B
Clocks
2.94912 GHz
2.94912 GHz
2.94912 GHz
2.94912 GHz
General
Purpose
Clocks
735 MHz
735 MHz
735 MHz
735 MHz
Package
RoHS-6,
Pb-Free
Temperature
Range
Ordering Part
Number
Refer-
ence
#
DSPLL
Number of
Clock In-
puts/
Outputs
4 / 12
4 / 12
4 / 12
4 / 12
Si5381A-E-GM
Si5382A-E-GM
Si5381E-E-GM
Si5382E-E-GM
Si5381E-E-EVB
Si5382E-E-EVB
External
External
Internal
Crystal
Internal
Crystal
4
2
4
2
64-Lead
9x9 mm
QFN
64-Lead
9x9 mm
LGA
Yes
–40 to +85 °C
Evaluation Board
Evaluation Board
Note:
1. Add an “R” at the end of the device to denote tape and reel options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by
ClockBuilder Pro.
Part number
format is: Si5381E-Exxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration.
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Preliminary Rev. 0.9 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Frequency Configuration . . . . . . . . . . . . .
3.1.1 Si5381/82 4G/LTE Frequency Configuration . . . .
3.1.2 Si5381/82 Configuration for Wireless Clock Generation .
3.1.3 DSPLL Loop Bandwidth . . . . . . . . . . .
3.1.4 Fastlock . . . . . . . . . . . . . . . . .
3.1.5 Modes of Operation . . . . . . . . . . . . .
3.1.6 Initialization and Reset . . . . . . . . . . . .
3.1.7 Free-run Mode . . . . . . . . . . . . . .
3.1.8 Lock Acquisition . . . . . . . . . . . . . .
3.1.9 Locked Mode . . . . . . . . . . . . . . .
3.1.10 Holdover Mode . . . . . . . . . . . . . .
3.2 External Reference (XA/XB) (Grade A Only)
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3.3 Inputs (IN0, IN1, IN2, IN3) . . . . . . . . .
3.3.1 Input Configuration and Terminations . . .
3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3) .
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3)
3.3.4 Hitless Input Switching . . . . . . . .
3.3.5 Glitchless Input Switching . . . . . . .
3.3.6 Zero Delay Mode (ZDM) . . . . . . .
3.4 Fault Monitoring . . . . . .
3.4.1 Input LOS Detection. . .
3.4.2 Reference LOS Detection .
3.4.3 OOF Detection . . . .
3.4.4 Precision OOF Monitor . .
3.4.5 Fast OOF Monitor . . .
3.4.6 LOL Detection . . . . .
3.4.7 Interrupt Pin INTRb . . .
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6
6
7
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8
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9
.10
.11
.12
.12
.13
.13
.13
.14
.15
.15
.15
.16
.16
.16
.17
.18
.18
.18
.18
.19
.19
.20
.20
.20
.20
.21
.21
.21
.21
.21
3.5 Outputs . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Output Crosspoint . . . . . . . . . . . . . . . .
3.5.2 Output Signal Format . . . . . . . . . . . . . . .
3.5.3 Output Terminations. . . . . . . . . . . . . . . .
3.5.4 Programmable Common Mode Voltage for Differential Outputs .
3.5.5 LVCMOS Output Terminations . . . . . . . . . . . .
3.5.6 LVCMOS Output Impedance and Drive Strength Selection. . .
3.5.7 LVCMOS Output Signal Swing . . . . . . . . . . . .
3.5.8 LVCMOS Output Polarity . . . . . . . . . . . . . .
3.5.9 Output Enable/Disable . . . . . . . . . . . . . . .
3.5.10 Output Disable During LOL . . . . . . . . . . . . .
3.5.11 Output Disable During Reference LOS (XAXB, Internal Crystal)
3.5.12 Output Driver State When Disabled . . . . . . . . . .
3.5.13 Synchronous Enable/Disable Feature . . . . . . . . .
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Preliminary Rev. 0.9 | 4
3.5.14 Output Divider (R) Synchronization .
3.6 Power Management . . . . .
3.6.1 Power Down Pin (PDNb) .
3.7 In-Circuit Programming .
3.8 Serial Interface
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.21
.21
.21
.21
.21
.22
3.9 Custom Factory Preprogrammed Devices
3.10 How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . .38
5. Electrical Specifications
6. Typical Application Diagram
7. Detailed Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . 39
. . . . . . . . . . . . . 40
8. Typical Operating Characteristics (Phase Noise and Jitter)
9. Pin Descriptions
10. Packages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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.45
.46
10.1 64-LGA Package .
10.2 64-QFN Package .
11. PCB Land Pattern
12. Top Marking
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1 Revision 0.9 .
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50
.50
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Preliminary Rev. 0.9 | 5
