Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72636
24-May-04
www.vishay.com
1
SPICE Device Model Si7423DN
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
b
Drain-Source On-State Resistance
b
Forward Transconductance
b
Diode Forward Voltage
b
Symbol
Test Conditions
Simulated
Data
1.8
60
0.014
0.023
29
−0.83
Measured
Data
Unit
V
GS(th)
I
D(on)
r
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
=
−250 µA
V
DS
=
−5
V, V
GS
=
−10
V
V
GS
=
−10
V, I
D
=
−11.7
A
V
GS
=
−4.5
V, I
D
=
−9
A
V
DS
=
−15
V, I
D
=
−11.7
A
I
S
=
−3.2
A, V
GS
= 0 V
V
A
0.014
0.023
29
−0.76
Ω
S
V
Dynamic
a
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
DD
=
−15
V, R
L
= 15
Ω
I
D
≅ −1
A, V
GEN
=
−10
V, R
G
= 6
Ω
V
DS
=
−15
V, V
GS
=
−10
V, I
D
=
−11.7
A
34
5.8
9.6
15
11
72
25
37.5
5.8
9.6
11
10
74
50
ns
nC
Notes
a. Guaranteed by design, not subject to production testing.
