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SiI100/SiI101 Datasheet

Silicon Image, Inc.

Version 1.1

June 1998

SiI/DS-0001-B

Silicon Image, Inc.

SiI/DS-0001-B

This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part

of this documentation without the express written permission of Silicon Image, Inc.

Trademark Acknowledgment

PanelLink

and TMDS

are trademarks of Silicon Image, Inc.

VESA® a registered trademark of Video Electronics Standards Association.

All other trademarks are the property of their respective holders.

Disclaimer

This document is provided for technical information for the user. Silicon Image, Inc. reserves the right to modify the

information in this document as necessary. The customer should make sure that it has the most recent data sheet version.

Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take

appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid

patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.

Revision 1.0

Subject to Change without Notice

Silicon Image, Inc.

SiI/DS-0001-B

Revision History

Revision

1.0

1.1

Date

8/97

6/98

Comment

Version 1.0 of SiI100/101 Datasheet

Version 1.1 of SiI100/101 Datasheet

Revision 1.0

Subject to Change without Notice

Silicon Image, Inc.

SiI/DS-0001-B

(This page left intentionally blank)

Revision 1.0

Subject to Change without Notice

Silicon Image, Inc.

SiI/DS-0001-B

Table of Contents

Revision History ..........................................................................................................................................................................3

Table of Contents.........................................................................................................................................................................5

List of Figures ..............................................................................................................................................................................6

List of Tables ...............................................................................................................................................................................7

1. Feature Review ........................................................................................................................................................................8

2. Product Summary.....................................................................................................................................................................9

3. Order Information ..................................................................................................................................................................10

PanelLink™

Technology Overview........................................................................................................................................11

5. SiI100 Overview ....................................................................................................................................................................12

5.1 Data Input ........................................................................................................................................................................13

6. SiI101 Overview ....................................................................................................................................................................14

6.1 Output Modes...................................................................................................................................................................16

6.1.1 One Pixel Per Clock Mode........................................................................................................................................16

6.1.2 Two Pixels Per Clock Mode .....................................................................................................................................16

6.2 Data Mapping (TFT) - VESA®

Compatible.......................................................................................................................17

6.2.1 One Pixel Per Clock Data Mapping ..........................................................................................................................17

6.2.2 Two Pixels Per Clock Data Mapping........................................................................................................................18

6.3 Output Clock Modes for 24-bit DSTN.............................................................................................................................19

6.4 Data Mapping (DSTN) - VESA®

Compatible .................................................................................................................20

7. TMDS Interconnect Layer .................................................................................................................................................22

7.1 Voltage Swing Control (EXT_SWING) ..........................................................................................................................23

7.2 Termination Control (EXT_RES) ....................................................................................................................................23

8. PLL Synchronization .............................................................................................................................................................24

9. SiI100 Pin Description...........................................................................................................................................................25

9.1 SiI100 Pin Diagram..........................................................................................................................................................25

9.2 SiI100 Pins Grouped by Functionality .............................................................................................................................26

9.2.1 SiI100 Input Pin Description.....................................................................................................................................26

9.2.2 SiI100 Test Output Pin Description ..........................................................................................................................27

9.2.3 SiI100 Synchronization Pin Description ...................................................................................................................27

9.2.4 SiI100 Configuration Pin Description.......................................................................................................................27

9.2.5 SiI100 Analog Data Pin Description.........................................................................................................................27

9.2.6 SiI100 Power and Ground Pin Description ...............................................................................................................28

9.3 SiI100 Pins Listed Numerically .......................................................................................................................................29

10. SiI101 Pin Description.........................................................................................................................................................31

10.1 SiI101 Pin Diagram........................................................................................................................................................31

10.2 SiI101 Pins Grouped by Functionality ...........................................................................................................................32

10.2.1 SiI101 Data Output Pin Description .......................................................................................................................32

10.2.2 SiI101 Test Output Pin Description ........................................................................................................................33

10.2.3 SiI101 Synchronization Pin Description .................................................................................................................33

10.2.4 SiI101 Analog Data Pin Description.......................................................................................................................33

10.2.5 SiI101 Configuration Pin Description.....................................................................................................................33

10.2.6 SiI101 Power and Ground Pin Description .............................................................................................................34

10.3 SiI101 Pins Listed Numerically .....................................................................................................................................35

11. Electrical Specifications.......................................................................................................................................................38

11.1 Absolute Conditions.......................................................................................................................................................38

11.2 DC Specifications ..........................................................................................................................................................39

11.3 AC Specifications ..........................................................................................................................................................40

11.4 Timing Diagrams ...........................................................................................................................................................41

11.4.1 SiI100 Input Timing................................................................................................................................................42

11.4.2 SiI101 Output Timing .............................................................................................................................................43

12. Package Dimensions ............................................................................................................................................................44

12.1 SiI100 Package Dimensions.............................................................................................................................................1

12.2 SiI101 Package Dimensions...........................................................................................................................................45

Revision 1.0

Subject to Change without Notice

型号	SII101CT80V360	SII100CT64V351
描述	Consumer Circuit, PQFP80, TQFP-80	Consumer Circuit, PQFP64, TQFP-64
厂商名称	Silicon image	Silicon image
零件包装代码	QFP	QFP
包装说明	TFQFP,	TFQFP,
针数	80	64
Reach Compliance Code	unknown	unknown
商用集成电路类型	CONSUMER CIRCUIT	CONSUMER CIRCUIT
JESD-30 代码	S-PQFP-G80	S-PQFP-G64
长度	12 mm	10 mm
端子数量	80	64
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFQFP	TFQFP
封装形状	SQUARE	SQUARE
封装形式	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH
认证状态	Not Qualified	Not Qualified
座面最大高度	1.15 mm	1.15 mm
最大压摆率	150 mA	150 mA
最大供电电压 (Vsup)	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V
表面贴装	YES	YES
温度等级	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm
端子位置	QUAD	QUAD
宽度	12 mm	10 mm
Base Number Matches	1	1