®
Technology
SiI 1161
PanelLink Receiver
Data Sheet
Document #
SiI-DS-0096-C
SiI
1161 PanelLink Receiver
Data Sheet
Silicon Image, Inc.
SiI-DS-0096-C
January 2004
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
Image web site at www.siimage.com, or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
is a registered trademark of the Video
Electronics Standards Association. All other trademarks are the property of their respective holders.
Trademark Acknowledgment
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision
SiI-DS-0096-0.80
SiI-DS-0096-0.91
SiI-DS-0096-A
SiI-DS-0096-B
SiI-DS-0096-C
Date
08/2002
06/2003
08/2003
11/2003
Comment
Advance Data Sheet.
Preliminary Data Sheet
Data Sheet
Data Sheet Rev B, page 3 - added V
OL
/ I
OL
spec for SDA pin; page 8 –
setup and hold time fixes; page 14 – hold time calculation fixes; page 36
– new signal trace routing example; page 40 – new part number added
Part marking spec updated
1/2004
© 2001, 2002, 2003, 2004 Silicon Image. Inc.
SiI-DS-0096-C
ii
SiI
1161 PanelLink Receiver
Data Sheet
TABLE OF CONTENTS
SiI
1161 Pin Diagram ....................................................................................................................1
Functional Description .................................................................................................................2
Electrical Specifications...............................................................................................................3
Absolute Maximum Conditions ................................................................................................................... 3
Normal Operating Conditions ..................................................................................................................... 3
Digital I/O Specifications ............................................................................................................................. 3
General DC Specifications .......................................................................................................................... 4
General AC Specifications .......................................................................................................................... 5
Compatibility Mode Selection Specifications.............................................................................6
SiI
161B (Compatible) Mode DC Specifications ......................................................................................... 6
SiI
161B (Compatible) Mode AC Specifications.......................................................................................... 8
SiI
1161 (Programmable) Mode DC Specifications .................................................................................... 9
SiI
1161 (Programmable) Mode AC Specifications................................................................................... 11
Timing Diagrams.........................................................................................................................15
Pin Descriptions..........................................................................................................................19
Output Pins ............................................................................................................................................... 19
Differential Signal Data Pins ..................................................................................................................... 19
Configuration Pins..................................................................................................................................... 20
Power Management Pins.......................................................................................................................... 20
Power and Ground Pins............................................................................................................................ 21
Feature Information ....................................................................................................................22
HSYNC De-jitter Function ......................................................................................................................... 22
Clock Detect Function............................................................................................................................... 22
OCK_INV Function ................................................................................................................................... 22
I
2
C Slave Interface .................................................................................................................................... 23
TFT Panel Data Mapping .......................................................................................................................... 24
Design Recommendations.........................................................................................................31
Differences Between
SiI
161B and
SiI
1161............................................................................................. 31
Using
SiI
1161 in Multiple-Input Applications............................................................................................ 31
Using
SiI
1161 to Replace TI TFP401 ...................................................................................................... 32
Adjusting Equalizer and Bandwidth .......................................................................................................... 32
Voltage Ripple Regulation......................................................................................................................... 33
Decoupling Capacitors.............................................................................................................................. 34
Series Damping Resistors on Outputs...................................................................................................... 35
Receiver Layout ........................................................................................................................................ 36
PCB Ground Planes.................................................................................................................................. 37
Staggered Outputs and Two Pixels per Clock .......................................................................................... 37
Adjusting Output Timings for Loading....................................................................................................... 37
Packaging ....................................................................................................................................38
Thermal Design Options ........................................................................................................................... 38
ePad Enhancement .................................................................................................................................. 38
Dimensions and Marking .......................................................................................................................... 40
Ordering Information ..................................................................................................................40
iii
SiI-DS-0096-C
SiI
1161 PanelLink Receiver
Data Sheet
LIST OF TABLES
Table 1. DC Parametric Specifications ........................................................................................................... 4
Table 2. General AC Specifications ................................................................................................................ 5
Table 3.
SiI
161B Mode DC Specifications ..................................................................................................... 7
Table 4.
SiI
161B Mode AC Specifications ..................................................................................................... 8
Table 5.
SiI
1161 Mode DC Specifications.................................................................................................... 10
Table 6.
SiI
1161 Mode AC Specifications .................................................................................................... 11
Table 7. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=0.................................... 13
Table 8. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=1.................................... 14
Table 9. One Pixel per Clock Mode Data Mapping....................................................................................... 24
Table 10. Two Pixel per Clock Mode Data Mapping..................................................................................... 24
Table 11. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2
TM
Compliant.................. 25
Table 12. Two Pixels per Clock Input/Output TFT Mode .............................................................................. 26
Table 13. 24-bit One Pixel per Clock Input with 24-bit Two Pixels per Clock Output TFT Mode ................. 27
Table 14. 18-bit One Pixel per Clock Input with 18-bit Two Pixels per Clock Output TFT Mode ................. 28
Table 15. Two Pixels per Clock Input with One Pixel per Clock Output TFT Mode ..................................... 29
Table 16. Output Clock Configuration by Typical TFT Panel Application ..................................................... 30
Table 17. New Pin Functions for
SiI
1161 in Programmable Mode .............................................................. 31
Table 18. Internal I
2
C Registers.................................................................................................................... 32
Table 19: I
2
C Register Field Definitions ........................................................................................................ 33
Table 20. Recommended Components for 1-2MHz Noise Suppression...................................................... 35
Table 21. Recommended Components for 100-200kHz Noise Suppression on PVCC .............................. 35
LIST OF FIGURES
Figure 1. Functional Block Diagram ............................................................................................................... 2
Figure 2.
SiI
161B Mode Control of Output Pin Drive Strength ...................................................................... 6
Figure 3. Output Loading in
SiI
161B Mode ................................................................................................... 9
Figure 4.
SiI
1161 Mode Control of Output Pin Drive Strength....................................................................... 9
Figure 5. Receiver Output Setup and Hold Times – OCK_INV=0................................................................ 12
Figure 6. Receiver Output Setup and Hold Times – OCK_INV=1................................................................ 13
Figure 7. Digital Output Transition Times ..................................................................................................... 15
Figure 8. Receiver Clock Cycle/High/Low Times ......................................................................................... 15
Figure 9. Channel-to-Channel Skew Timing ................................................................................................ 15
Figure 10. Receiver Clock-to-Output Delay and Duty Cycle Limits ............................................................. 16
Figure 11. Output Signals Disabled Timing from Clock Inactive .................................................................. 16
Figure 12. Wake-Up on Clock Detect .......................................................................................................... 16
Figure 13. Output Signals Disabled Timing from PD# Active ....................................................................... 17
Figure 14. SCDT Timing from DE Inactive or Active .................................................................................... 17
Figure 15. Two Pixels per Clock Staggered Output Timing Diagram ........................................................... 17
Figure 16. I
2
C Data Valid Delay (driving Read Cycle data) .......................................................................... 18
Figure 17. Block Diagram for OCK_INV....................................................................................................... 22
Figure 18. I
2
C Byte Read.............................................................................................................................. 23
Figure 19. I
2
C Byte Write .............................................................................................................................. 23
Figure 20. Voltage Regulation using TL431 ................................................................................................. 33
Figure 21. Voltage Regulation using LM317 ................................................................................................ 34
Figure 22. Decoupling and Bypass Capacitor Placement............................................................................ 34
Figure 23. Decoupling and Bypass Schematic............................................................................................. 35
Figure 24. Receiver Output Series Damping Resistors ............................................................................... 35
Figure 25. General Signal Routing Recommendations................................................................................ 36
Figure 26. Signal Trace Routing Example.................................................................................................... 36
Figure 27. ePad Diagram ............................................................................................................................. 38
Figure 28. Temperature Rise with Frequency and ePad.............................................................................. 39
Figure 29. Package Diagram........................................................................................................................ 40
SiI-DS-0096-C
iv
SiI
1161 PanelLink Receiver
Data Sheet
General Description
The
SiI
1161 receiver uses PanelLink Digital
technology to support high-resolution displays up to
UXGA (25-165MHz). This receiver supports up to true
color panels (24 bits per pixel, 16M colors) with both
one and two pixels per clock.
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the
same logical interface. System designers can be
assured that the interface will be stable through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a digital
interface solution that is quicker to market and lower in
cost.
Features
•
•
•
•
•
•
•
•
•
•
•
January 2004
Supports 10 meter cables at UXGA speed
I
2
C port for dynamic optimization of settings to
compensate for long cables and/or poor quality
transmitters
Flexible output drive controls to optimize timings
for all possible configurations
3.3V operation
Time staggered data output for reduced ground
bounce and lower EMI
Sync Detect feature for DVI “Hot Plugging”
ESD tolerant to 5kV (HBM) on all pins
Compliant with DVI 1.0
Guaranteed interoperability with DVI-compliant
transmitters
Low power standby mode; automatic entry into
standby mode with clock detect circuitry
Lead-free packaging (see page 40).
SiI
1161 Pin Diagram
ODD 8-bits RED
QO22
75
QO21
74
QO20
73
QO19
72
QO18
71
QO17
70
QO16
69
QO15
GND
68
VCC
67
ODD 8-bits GREEN
OGND
OVCC
QO14
65
QO13
QO12
QO11
QO10
QO9
60
QO8
59
QO7
QO6
ODD 8-bits BLUE
QO5
QO4
QO3
QO2
57
58
56
55
54
53
52
51
66
64
63
62
61
OGND
QO23
OVCC
AGND
RX2+
RX2-
AVCC
AGND
AVCC
RX1+
RX1-
AGND
AVCC
AGND
SIGNAL
PLL
RX0+
RX0-
AGND
RXC+
RXC-
AVCC
EXT_RES
PVCC
PGND
MODE
SCL
(OCK_INV)
DIFFERENTIAL
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
14
15
16
17
20
21
22
23
24
25
18
19
6
1
HS_DJTR
2
PD#
3
SDA (ST)
7
9
5
GND
4
PIXS
8
SCDT
50
49
48
47
46
45
44
43
QO1
QO0
CONTROLS
HSYNC
VSYNC
DE
OGND
ODCK
OVCC
CTL3
GPO
CTL2
CTL1
GND
VCC
QE23
QE22
EVEN 8-bits RED
QE21
QE20
QE19
QE18
QE17
QE16
OVCC
OGND
QE15
QE14
OUTPUT
CLOCK
SiI
1161
100-Pin
TQFP
(Top View)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
I2C_MODE#
(STAG_OUT#)
VCC
CONFIG. PINS
PWR
MGMT
PDO#
QE0
QE1
EVEN 8-bits BLUE
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
OVCC
OGND
EVEN 8-bits GREEN
SiI-DS-0096-C
嵌入式系统
