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SiI 1178

Dual Link

PanelLink Transmitter

Data Sheet

Document # SiI-DS-0127-A

SiI 1178

PanelLink Transmitter

Data Sheet

Silicon Image, Inc.

SiI-DS-0127-A

September 2005

Application Information

To obtain the most updated Application Notes and other useful information for your design, contact your local

Silicon Image sales office. Please also visit the Silicon Image web site at

www.siliconimage.com.

This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or

send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.

Silicon Image, the Silicon Image logo, PanelLink

and the PanelLink

Digital logo are registered trademarks of

Silicon Image, Inc. TMDS

is a trademark of Silicon Image, Inc. VESA

is a registered trademark of the Video

Electronics Standards Association. All other trademarks are the property of their respective holders.

Trademark Acknowledgment

Disclaimer

This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the

information in this document as necessary. The customer should make sure that they have the most recent data

sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.

Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.

Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to

infringe upon such rights.

Revision History

Revision

Date

09/20/05

Comment

Data Sheet

SiI-DS-0127-A

SiI 1178

PanelLink Transmitter

Data Sheet

TABLE OF CONTENTS

Functional Description .................................................................................................................................... 2

Data Capture Logic ..................................................................................................................................... 2

PanelLink TMDS Core ................................................................................................................................ 2

C Slave Machine, Registers, and Configuration Logic............................................................................. 3

Hot Plug Logic............................................................................................................................................. 3

Electrical Specifications .................................................................................................................................. 4

Absolute Maximum Conditions ................................................................................................................... 4

Normal Operating Conditions ..................................................................................................................... 4

DC Specifications........................................................................................................................................ 5

AC Specifications ........................................................................................................................................ 6

Timing Diagrams ......................................................................................................................................... 7

Input Timing Diagrams ................................................................................................................................ 7

Pin Descriptions.............................................................................................................................................. 9

Input Pins .................................................................................................................................................... 9

Status Pin .................................................................................................................................................. 10

Configuration/Programming Pins.............................................................................................................. 10

Input Voltage Reference Pin ..................................................................................................................... 10

Output and Differential Signal Data Pins .................................................................................................. 11

Dual Link Configuration and Control Pin................................................................................................... 11

Power and Ground Pins............................................................................................................................ 11

Feature Information ...................................................................................................................................... 12

C Interface .............................................................................................................................................. 12

C Register Mapping ................................................................................................................................ 13

RESET Description ................................................................................................................................... 15

Dual Zone PLL .......................................................................................................................................... 15

Manual Zone Control............................................................................................................................. 15

Automatic Zone Control......................................................................................................................... 16

Input Signal Swing and Clocking Selection .............................................................................................. 16

EDGE Selection ........................................................................................................................................ 17

Data De-skew DK[1:0] Feature ................................................................................................................. 18

Dual Link Applications............................................................................................................................... 19

Master Configuration ............................................................................................................................. 20

Slave Configuration ............................................................................................................................... 20

Master-Slave Skew Control ...................................................................................................................... 20

Data Mapping Modes for Dual Link .............................................................................................................. 21

Dual Link I

C Programming Sequence Example ...................................................................................... 23

Timing Diagrams ....................................................................................................................................... 23

Enabling Hot Plug Detection Mode........................................................................................................... 24

Design Recommendations ........................................................................................................................... 25

Overview of Pin Differences...................................................................................................................... 25

1.5V to 3.3V I

C Bus Level-Shifting .......................................................................................................... 25

ESD Protection on TMDS Output Pins ..................................................................................................... 26

Voltage Ripple Regulation......................................................................................................................... 27

PCB Ground Planes.................................................................................................................................. 27

Decoupling Capacitors.............................................................................................................................. 27

Source Termination Resistors on Differential Outputs .............................................................................. 28

Transmitter Layout .................................................................................................................................... 30

Recommended Circuits............................................................................................................................. 32

Packaging ..................................................................................................................................................... 33

E-pad Enhancement ................................................................................................................................. 33

Determining Heat Dissipation Requirements ........................................................................................ 33

Designing with E-pad Landing Area ...................................................................................................... 34

48-pin TSSOP Package ............................................................................................................................ 35

Ordering Information ................................................................................................................................. 35

SiI-DS-0127-A

iii

SiI 1178

PanelLink Transmitter

Data Sheet

LIST OF TABLES

Table 1. General I

C Register Definitions ..................................................................................................... 14

Table 2. Dual Link I

C Register Definitions................................................................................................... 15

Table 3. Dual Zone PLL I

C Control Register Bits ........................................................................................ 16

Table 4. DK[1:0] Increments and Effect on Setup and Hold times .............................................................. 18

Table 5. Dual Link Data Mapping – High Resolution Application ................................................................. 21

Table 6. Dual Link Data Mapping – 10-bit Deep Color Application .............................................................. 22

Table 7. Dual Link Programming Sequence and Flowchart ......................................................................... 23

Table 8. Recommended Components for 1-2MHz Noise Suppression........................................................ 28

Table 9. DVI Connector to

SiI

1178 Tx for Dual Link Pin Connection .......................................................... 31

Table 10. Allowed Power Consumption vs. E-Pad Solder State................................................................... 34

LIST OF FIGURES

Figure 1.

SiI

1178 Tx Pin Diagram.................................................................................................................. 1

Figure 2. Functional Block Diagram ............................................................................................................... 2

Figure 3. Clock Cycle/High/Low Times in High Swing Mode ......................................................................... 7

Figure 4. Differential Transition Times ............................................................................................................ 7

Figure 5.

VSYNC, HSYNC Delay Times to DE

.................................................................................................... 7

Figure 6. DE High/Low Times......................................................................................................................... 7

Figure 7. Low Swing Control and Data Setup/Hold Times to IDCK± Differential Clock ................................. 8

Figure 8. High Swing Control and Data Setup/Hold Times to IDCK+ ............................................................ 8

Figure 9. I

C Data Valid Delay (driving Read Cycle data) .............................................................................. 8

Figure 10. RST# Minimum Timing .................................................................................................................. 8

Figure 11. I

C Byte Read .............................................................................................................................. 12

Figure 12. I

C Byte Write .............................................................................................................................. 12

Figure 13. Logical Interface Options for 12-bit Mode ................................................................................... 17

Figure 14. De-skewing Feature Timing ........................................................................................................ 18

Figure 15. Dual Link Configuration............................................................................................................... 19

Figure 16. Single/Dual Link Timing Diagram ................................................................................................ 24

Figure 17. I

C Bus Voltage Level-Shifting using Fairchild NDC7002N ........................................................ 25

Figure 18. I

C Bus Voltage Level Shifting using Philips GTL 2010 .............................................................. 26

Figure 19. ESD Protection Circuit ................................................................................................................ 26

Figure 20. Voltage Regulation using LM317EMP......................................................................................... 27

Figure 21. Decoupling and Bypass Capacitor Placement............................................................................ 27

Figure 22. Decoupling and Bypass Schematic............................................................................................. 28

Figure 23. Differential Output Source Terminations ..................................................................................... 28

Figure 24. Source Termination Layout Illustration ........................................................................................ 29

Figure 25. Transmitter to DVI Connector Layout.......................................................................................... 30

Figure 26. Recommended Hot Plug Connection.......................................................................................... 32

Figure 27. E-pad Diagram ............................................................................................................................ 33

Figure 28. Package Diagram........................................................................................................................ 35

SiI-DS-0127-A

SiI

1178 PanelLink Transmitter

Data Sheet

September 2005

General Description

The

SiI

1178 transmitter uses PanelLink Digital

technology to support displays ranging from single link

resolutions of VGA to UXGA resolution (25 - 165Mpps)

and dual link resolutions of up to QUXGA (330Mpps).

The

SiI

1178 Tx is pin-compatible with the SiI 1178 Tx,

supporting 12-bit mode (½ pixel per clock edge at

double data rates) for true color (16.7 million) support..

Input jitter tolerance is greatly enhanced over the SiI

1178 Tx, enabling spread spectrum applications.

Single-clock/dual-edge clocking is supported in both

high swing and low swing modes.

Used in pairs,

SiI

1178 transmitters support dual link

mode and allow dynamic switching between single link

and dual link operation by way of their I

C interfaces.

PanelLink Digital technology simplifies PC design by

resolving many of the system level issues associated

with high-speed mixed signal design, providing the

system designer with a digital interface solution that is

quicker to market and lower in cost.

Features

•

Scaleable bandwidth:

Single link operation from 25 - 165 Mega-

pixels per second (VGA to UXGA)

Dual link operation up to 330 Mega-pixels

per second

12-bit (½ pixel) DDR input with flexible input

clocking: Single-clock/dual-edge or dual-

clock/single-edge

Full support for low swing DVO 2.0 mode

C slave programming interface

Selectable input level voltage swing:

Low voltage interface: 1.0 to 1.9V

High swing interface: 3.3V

Monitor detection supported through Hot Plug

and receiver sense

Cable distance support: Over 10m

Compliant with DVI 1.0

Space saving and environmentally safe 48-pin

TSSOP Pb-free package

•

SYNCO/SYNCI

EXT_SWING

PVCC2

HTPLG

MSEN

PGND

AGND

PVCC1

AGND

PGND

AVCC

TXC+

TX1+

TX0+

TX0-

TX1-

GND

SiI

1178 Tx

48-Pin TSSOP

(Top View)

IDCK-

Figure 1.

SiI

1178 Tx Pin Diagram

SiI-DS-0127-A

CTL3/A1

D11

D10

IDCK+

VREF

VSYNC

GND

VCC

HSYNC

VCC

RST#

TX2+

TXC-

TX2-

SDA

SCL

型号	SII1178CSU
描述	Consumer Circuit, PDSO48, LEAD FREE, MO-153, TSSOP-48
是否无铅	不含铅
是否Rohs认证	符合
零件包装代码	TSSOP
包装说明	TSSOP,
针数	48
Reach Compliance Code	compliant
ECCN代码	EAR99
商用集成电路类型	CONSUMER CIRCUIT
JESD-30 代码	R-PDSO-G48
长度	9.7 mm
功能数量	1
端子数量	48
最高工作温度	70 °C
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	1.1 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
表面贴装	YES
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.4 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	4.4 mm
Base Number Matches	1