®
Technology
SiI 1362/A & SiI 1364/A
SDVO PanelLink Transmitter
Data Sheet
Document #
SiI-DS-0112-B1
SiI
1362/A &
SiI
1364/A PanelLink Transmitter
Data Sheet
Silicon Image, Inc.
SiI-DS-0112-B1
March 2006
Application Information
To obtain the most updated Application Notes and other useful information for your design, visit the Silicon Image
web site at www.siliconimage.com or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Silicon Image, the Silicon Image logo, PanelLink
®
, TMDS
®
and the PanelLink
®
Digital logo are registered
trademarks of Silicon Image, Inc. VESA
®
is a registered trademark of the Video Electronics Standards
Association. I
2
C is a trademark of Philips Semiconductor. Intel
®
is a registered trademark of Intel Corp. SDVO
(Serial Digital Video Output) is a data format proprietary to Intel Corporation for use by Intel Graphics Chipsets.
All other trademarks are the property of their respective holders.
Trademark Acknowledgment
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision
A
A1
A2
B
B1
Date
07/04
08/05
08/05
10/05
03/06
Comment
Revision A Release
Added 1362A and 1364A part number.
Adjusted 64 pin A1 & A2 overlap.
Added SiI 1362A & 1364A new power numbers. Updated PVCC1 Voltage range
to 3.30V + 10%. Voltage Regulation for PVCC1 omitted for SiI 1362A & SiI
1364A.
Included new QFN package dimensions and ordering number.
© 2004-2006 Silicon Image. Inc.
ii
SiI-DS-0112-B1
SiI
1362/A &
SiI
1364/A PanelLink Transmitter
Data Sheet
TABLE OF CONTENTS
General Description ..................................................................................................................................... 1
SiI
1362/A &
SiI
1364/A Pin Diagrams........................................................................................................ 1
Functional Blocks......................................................................................................................................... 3
PanelLink TMDS Digital Core ..................................................................................................................... 3
SDVO Receiver Core.................................................................................................................................. 3
I
2
C Slave Interface and Display Detection.................................................................................................. 4
Electrical Specifications .............................................................................................................................. 5
Absolute Maximum Conditions ................................................................................................................... 5
Normal Operating Conditions ..................................................................................................................... 5
DC Digital I/O Specifications....................................................................................................................... 5
DC Specifications........................................................................................................................................ 6
AC Specifications........................................................................................................................................ 6
Input Timing Diagrams................................................................................................................................. 7
Pin Descriptions ........................................................................................................................................... 8
SDVO Receiver Core Pins.......................................................................................................................... 8
Configuration/Programming Pins................................................................................................................ 8
Differential Signal Data Pins ....................................................................................................................... 9
I
2
C Master Interface Pins ............................................................................................................................ 9
Factory Test Mode Pins .............................................................................................................................. 9
Power and Ground Pins............................................................................................................................ 10
Feature Information.................................................................................................................................... 11
I
2
C Slave Interface .................................................................................................................................... 11
Design Recommendations ........................................................................................................................ 12
EXT_SWING Selection ............................................................................................................................. 12
EXT_RES Selection.................................................................................................................................. 12
SDVO I
2
C Bus Interface............................................................................................................................ 12
DDC I
2
C Bus Interface .............................................................................................................................. 12
EEPROM I
2
C Bus Interface ...................................................................................................................... 13
PCB Ground Planes.................................................................................................................................. 13
Power Plane Sequencing and Switching .................................................................................................. 13
Voltage Ripple Regulation ........................................................................................................................ 13
Power Plane Filters................................................................................................................................... 16
Filter Capacitor and Ferrite Placement ................................................................................................. 16
Source Termination Resistors on Differential Outputs ............................................................................. 17
Transmitter Layout .................................................................................................................................... 18
Hot Plug Circuit ......................................................................................................................................... 20
Package Dimensions and Marking Specification.................................................................................... 21
64-pin TQFP Ordering Information ........................................................................................................... 21
64-pin QFN Ordering Information ............................................................................................................. 22
48-pin Ordering Information ...................................................................................................................... 23
SiI-DS-0112-B1
iii
SiI
1362/A &
SiI
1364/A PanelLink Transmitter
Data Sheet
LIST OF TABLES
Table 1. SDVO Clock Multiplication ............................................................................................................... 4
Table 2. Absolute Maximum Conditions......................................................................................................... 5
Table 3. Normal Operating Conditions ........................................................................................................... 5
Table 4. DC Digital I/O Specifications ............................................................................................................ 5
Table 5. DC Specifications ............................................................................................................................. 6
Table 6. AC Specifications ............................................................................................................................. 6
Table 7. Power Regulator Circuit Suggestions ............................................................................................ 13
Table 8. Power Plane Filter Recommendations for
SiI
1362/A &
SiI
1364/A............................................... 16
Table 9. Routing Guidelines for DVI Traces................................................................................................. 19
LIST OF FIGURES
Figure 1. SiI 1362/A Pin Diagram - 48-pin package ...................................................................................... 1
Figure 2. SiI 1364/A Pin Diagram - 64-pin package ...................................................................................... 2
Figure 3. Functional Block Diagram ............................................................................................................... 3
Figure 4. I
2
C Data Valid Delay (driving Read Cycle data).............................................................................. 7
Figure 5. RESET# Minimum Timing ............................................................................................................... 7
Figure 6. I
2
C Byte Read................................................................................................................................ 11
Figure 7. I
2
C Byte Write ................................................................................................................................ 11
Figure 8. Variation of Differential Swing versus R
EXT_SWING
Value................................................................ 12
Figure 9. Suggested 3.42V Voltage Supply Circuit for SiI 1362 and SiI 1364 only...................................... 14
Figure 10. Suggested 5V Voltage Supply Circuit ......................................................................................... 14
Figure 11. Suggested 1.8V Voltage Supply Circuit ...................................................................................... 15
Figure 12. Suggested 2.5V Voltage Supply Circuit ...................................................................................... 15
Figure 13. Decoupling and Bypass Capacitor Placement............................................................................ 16
Figure 14. Differential Output Source Terminations .................................................................................... 17
Figure 15. Source Termination Layout Illustration ....................................................................................... 17
Figure 16. Example of Incorrect Differential Signal Routing ........................................................................ 18
Figure 17. Example of Correct Differential Signal Routing........................................................................... 19
Figure 18. Source Termination to DVI Connector Illustration....................................................................... 19
Figure 19. Recommended Hot Plug Connection.......................................................................................... 20
Figure 20. 64-pin TQFP Package Dimensions............................................................................................. 21
Figure 21. 64-pin QFN Package Dimensions and ePad Diagram ............................................................... 22
Figure 22. 48-pin LQFP Package Dimensions............................................................................................. 23
iv
SiI-DS-0112-B1
SiI
1362/A &
SiI
1364/A PanelLink Transmitter
Data Sheet
General Description
The
SiI
1362/A &
SiI
1364/A TMDS transmitter uses
PanelLink
®
Digital technology to support displays
ranging from VGA to UXGA resolutions in a single
link interface. The chip supports the Intel-proprietary
SDVO serial interface to provide a display interface
to DVI monitors.
Designed explicitly to accommodate the ultra high-
speeds needed for SDVO signaling, the
SiI
1362/A
&
SiI
1364/A transmitter reduces pin count yet
provides an upgrade path for future feature
expansion. The innovative design of the
SiI
1362/A
&
SiI
1364/A eases board design requirements as
well.
PanelLink Digital technology simplifies PC design by
resolving many of the system level issues
associated with high-speed mixed signal design,
providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
Features
•
•
•
•
•
Scaleable Output Bandwidth: 25 - 165 megapixels
per second
SiI
1362/1364 fully compliant with Intel SDVO 1.0
SiI
1362A/1364A fully compliant with Intel SDVO 1.1
I
2
C Slave interface for access to internal registers
Dual I
2
C pass-through interfaces for host I
2
C access
of EDID (via DDC) and configuration EEPROM (on
64-pin package only)
Monitor Detection supported through Hot Plug or
Receiver Sense
Low Power: 1.8V core operation; power down mode
Cable Distance Support: greater than 10 meters
DVI 1.0 compliant, with significantly greater margin
than competitive solutions
SiI
1362/A: 48-pin LQFP without EEPROM interface
SiI
1364: 64-pin TQFP package with EEPROM
interface
SiI
1364A: 64-pin TQFP or QFN package with
EEPROM interface.
•
•
•
•
•
•
•
SiI
1362/A &
SiI
1364/A Pin Diagrams
SDVO Interrupt
EXT_RES
35
Filter PLL
EXT_SWING
PGND2
HTPLG
PVCC2
SVCC
36
TEST
SDI+
GND
VCC
34
VCC
SDI-
33
32
31
30
29
28
27
26
25
Red
SDR+
SDR-
SGND
SDG+
37
38
39
40
41
42
43
44
45
46
47
48
10
12
11
2
3
4
5
7
8
9
6
1
24
23
22
21
20
AGND
TX2+
TX2-
AVCC
TX1+
TX1-
AGND
TX0+
TX0-
AVCC
TXC+
TXC-
Green
SDG-
SVCC
SDB+
SDVO
Interface
Blue
SiI 1362/A
Tx
48-Pin LQFP
(Top View)
19
18
17
16
15
14
13
DVI
Interface
SDB-
SGND
SDC+
Clock
SDC-
SPVCC
Figure 1. SiI 1362/A Pin Diagram - 48-pin package
SiI-DS-0112-B1
1
OVCC
RESET#
SPGND
I
2
C from
SDVO
SDSDA
SDSCL
A1
GND
SCLDDC
I
2
C to
DDC
SDADDC
VCC
Main TMDS
PLL
PVCC1
AGND
