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SII160CTG100

Consumer Circuit, CMOS, PQFP100, LEAD FREE, MS-026ED, TQFP-100

器件类别：其他集成电路（IC）    消费电路   

厂商名称：Silicon image

厂商官网：http://www.siliconimage.com/

器件标准：  

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参数 预览 参数对比
器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
QFP
包装说明
TFQFP, TQFP100,.63SQ
针数
100
Reach Compliance Code
compliant
商用集成电路类型
CONSUMER CIRCUIT
JESD-30 代码
S-PQFP-G100
长度
14 mm
功能数量
1
端子数量
100
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
TFQFP
封装等效代码
TQFP100,.63SQ
封装形状
SQUARE
封装形式
FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）
NOT SPECIFIED
电源
3.3 V
认证状态
Not Qualified
座面最大高度
1.2 mm
最大压摆率
110 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
GULL WING
端子节距
0.5 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
14 mm
Base Number Matches
1
文档预览
®
Technology
SiI 160
PanelLink Transmitter
Data Sheet
Document #
SiI-DS-0008-F
SiI
160 PanelLink Transmitter
Data Sheet
Silicon Image, Inc.
SiI-DS-0008-F
August 2002
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
Image web site at www.siliconimage.com or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
, FPDI
TM
are trademarks of the Video
Electronics Standards Association. I
2
C is a trademark of Philips Semiconductor. All other trademarks are the
property of their respective holders.
Trademark Acknowledgment
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision
A
B
C
D
E
F
Date
01/99
03/99
04/00
07/00
03/02
08/02
Comment
Revision A release
Revision B Release
Revision C Release
Revision D Release
New Document format. Added PVCC power design guidelines &
series input termination. TFT mapping info appended.
Added Pb-Free package ordering information. Changed all Vih
and Vil levels to CMOS levels.
2002 Silicon Image. Inc.
SiI-DS-0008-F
ii
SiI
160 PanelLink Transmitter
Data Sheet
TABLE OF CONTENTS
General Description........................................................................................................................................ 1
Features ...................................................................................................................................................... 1
SiI 160
Pin Diagram........................................................................................................................................ 1
Functional Description .................................................................................................................................... 2
Electrical Specifications .................................................................................................................................. 3
Absolute Maximum Conditions ................................................................................................................... 3
Normal Operating Conditions ..................................................................................................................... 3
Digital I/O Specifications ............................................................................................................................. 3
DC Specifications........................................................................................................................................ 4
AC Specifications ........................................................................................................................................ 5
Input Timing Diagrams ................................................................................................................................ 6
Pin Descriptions.............................................................................................................................................. 8
Input Pins .................................................................................................................................................... 8
Configuration Pins....................................................................................................................................... 8
Power Management Pins............................................................................................................................ 8
Differential Signal Data Pins ....................................................................................................................... 9
Reserved Pins............................................................................................................................................. 9
Power and Ground Pins.............................................................................................................................. 9
TFT Panel Data Mapping.............................................................................................................................. 10
Design Recommendations ........................................................................................................................... 15
Voltage Ripple Regulation......................................................................................................................... 15
Decoupling Capacitors.............................................................................................................................. 16
Series Damping Resistors on Outputs...................................................................................................... 17
Differential Trace Routing ......................................................................................................................... 17
Package Dimensions.................................................................................................................................... 19
Ordering Information..................................................................................................................................... 19
LIST OF TABLES
Table 1. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 Compliant.............................. 10
Table 2. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 11
Table 3. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode................................ 12
Table 4. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode................................ 13
Table 5. Two Pixels/Clock Input with One Pixel/Clock Output TFT Mode .................................................... 14
Table 6. Recommended Components for Bypass and Decoupling Circuits................................................. 16
LIST OF FIGURES
Figure 1. Pin Diagram for
SiI
160 ................................................................................................................... 1
Figure 2. Functional Block Diagram ............................................................................................................... 2
Figure 3. Clock Cycle High/Low Times........................................................................................................... 6
Figure 4. Small Swing Differential Times........................................................................................................ 6
Figure 5. Input Data Setup/Hold Time to IDCK .............................................................................................. 7
Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE ...................................................................... 7
Figure 7. DE High and Low Times.................................................................................................................. 7
Figure 8. Voltage Regulation using TL431 ................................................................................................... 15
Figure 9. Voltage Regulation using LM317 .................................................................................................. 15
Figure 10. Decoupling and Bypass Capacitor Placement............................................................................ 16
Figure 11. Decoupling and Bypass Schematic............................................................................................. 16
Figure 12. Series Input Damping Resistors for Driving Source ................................................................... 17
Figure 13. Example of incorrect Differential Signal Routing......................................................................... 17
Figure 14. Example of correct Differential Signal Routing ........................................................................... 18
Figure 15. Differential Trace Routing to DVI Connector(Top Side View) ..................................................... 18
Figure 16. 100-pin TQFP Package Dimensions (JEDEC code MS-026ED)................................................ 19
iii
SiI-DS-0008-F
SiI
160 PanelLink
®
Transmitter
Data Sheet
General Description
The
SiI
160 transmitter uses PanelLink Digital
technology to support displays up to UXGA
resolution). The
SiI
160 transmitter supports up to true
color panels (24bit/pixel, 16.7M colors) in 1 or 2
pixels/clock mode.
All PanelLink products are designed on scaleable
CMOS architecture to support future performance
requirements while maintaining the same logical
interface. With this architecture system designers can
be assured that the interface will be fixed through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC & display
interface design by resolving many of the system level
issues associated with high-speed digital design,
providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
August 2002
Features
•
•
•
•
•
•
•
•
Scaleable Bandwidth: 25-165 MHz (VGA to
UXGA)
Low Power: 110mA max power consumption at
3.3V core operation
High Skew Inter pair Tolerance: 1 full input clock
cycle (6ns at 165 MHz)
Flexible panel interface: single or dual pixel in at
up to 24-bits
Cable Distance Support: over 5m DVI cable
Full VESA
TM
P&D, FPDI-2
TM
and DVI 1.0
compliant
Advanced on-chip input clock jitter filter to ensure
clean output to receiver
Available in Standard or Pb-Free (Environment
friendly) package (see page 19)
SiI 160
Pin Diagram
EXT_SWING
ODD 8-bits RED
DIO20
51
25
PIXS
DIO19
52
24
EDGE
DIO18
53
23
RSVD
DIO17
54
22
RSVD
DIO16
55
21
RSVD
VCC
56
20
RSVD
DIO15
58
18
PVCC1
DIO14
ODD 8-bits
GREEN
59
17
IVCC
DIO13
60
16
DIE0
DIO11
62
DIO10
63
SiI
160
100-Pin TQFP
(Top View)
14
DIE2
13
DIE3
DIO9
64
12
DIE4
DIO8
65
11
DIE5
IVCC
66
10
DIE6
GND
67
9
DIE7
DIO7
ODD 8-bits BLUE
68
8
VCC
DIO6
69
7
GND
DIO5
70
6
DIE8
DIO4
71
5
DIE9
DIO2
73
3
DIE11
DIO1
DIO0
74
76
2
77
DIE12
78
79
80
IVCC
81
82
83
84
85
86
87
88
HSYNC
GND
PGND2
CTL2
CTL1
PVCC2
CTL3
GND
89
90
91
92
93
94
95
96
97
IVCC
98
99
RSVD
VSYNC
DIE23
CONTROLS
INPUT CLOCK
GPI
PLL
Figure 1. Pin Diagram for
SiI
160
DIE22
EVEN 8-bits RED
DIE21
DIE20
DIE19
DIE18
DIE17
DIE16
DIE15
DIE14
IDCK
VCC
DE
100
75
1
DIE13
1
SiI-DS-0008-F
EVEN 8-bits GREEN
DIO3
72
4
DIE10
EVEN 8-bits BLUE
DIO12
61
15
DIE1
PLL
GND
57
19
PGND1
CONFIG. PINS
DIFFERENTIAL
SIGNAL
DIO21
DIO22
DIO23
AGND
AGND
AGND
AGND
AVCC
AVCC
AVCC
TX2+
TX1+
TX0+
TXC+
TXC-
TX2-
TX1-
TX0-
GND
VCC
RSVD
RSVD
RSVD
27
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
26
PD
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参数对比
与SII160CTG100相近的元器件有：SII160CT100。描述及对比如下：
型号 SII160CTG100 SII160CT100
描述 Consumer Circuit, CMOS, PQFP100, LEAD FREE, MS-026ED, TQFP-100 Consumer Circuit, CMOS, PQFP100, MS-026ED, TQFP-100
是否Rohs认证 符合 不符合
零件包装代码 QFP QFP
包装说明 TFQFP, TQFP100,.63SQ TFQFP, TQFP100,.63SQ
针数 100 100
Reach Compliance Code compliant unknown
商用集成电路类型 CONSUMER CIRCUIT CONSUMER CIRCUIT
JESD-30 代码 S-PQFP-G100 S-PQFP-G100
长度 14 mm 14 mm
功能数量 1 1
端子数量 100 100
最高工作温度 70 °C 70 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TFQFP TFQFP
封装等效代码 TQFP100,.63SQ TQFP100,.63SQ
封装形状 SQUARE SQUARE
封装形式 FLATPACK, THIN PROFILE, FINE PITCH FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED
电源 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified
座面最大高度 1.2 mm 1.2 mm
最大压摆率 110 mA 110 mA
最大供电电压 (Vsup) 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V
表面贴装 YES YES
技术 CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL
端子形式 GULL WING GULL WING
端子节距 0.5 mm 0.5 mm
端子位置 QUAD QUAD
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED
宽度 14 mm 14 mm
Base Number Matches 1 1
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器件捷径:
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