®
Technology
SiI 164
PanelLink Transmitter
Data Sheet
Document # SiI-DS-0021-E.doc
SiI
164 PanelLink Transmitter
Data Sheet
Silicon Image, Inc.
SiI-DS-0021-E
June 2005
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
Image web site at www.siliconimage.com or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
, FPD
TM
are trademarks of the Video
Electronics Standards Association. I
2
C is a trademark of Philips Semiconductor. All other trademarks are the
property of their respective holders.
Trademark Acknowledgment
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision
SiI-DS-0021-A
SiI-DS-0021-B
SiI-DS-0021-C
Date
01/99
03/99
04/02
Comment
Full Release
Internal Revision B release
New format. I
2
C programming and strapping mode
description,TFT mapping and Design Recommendations,
pin names ISEL/RST changed to ISEL/RST# and PD to
PD#.
Included Pb-free package. Added De-skew range.
Corrected PD# pin number.
Corrected D1 dimension. Corrected JEDEC code.
Included VCC details for power measurement. Added
Register Reset values and additional sample programming
code.
SiI-DS-0021-D
SiI-DS-0021-E
09/02
06/05
© 2005 Silicon Image, Inc.
SiI-DS-0021-E
ii
SiI
164 PanelLink Transmitter
Data Sheet
TABLE OF CONTENTS
General Description........................................................................................................................................ 1
Features ...................................................................................................................................................... 1
SiI
164 Pin Diagram ....................................................................................................................................... 1
Functional Description .................................................................................................................................... 2
PanelLink TMDS Digital Core ..................................................................................................................... 2
I
2
C Interface and Registers......................................................................................................................... 2
Data Capture Logic ..................................................................................................................................... 3
Electrical Specifications .................................................................................................................................. 4
Absolute Maximum Conditions ................................................................................................................... 4
Normal Operating Conditions ..................................................................................................................... 4
Digital I/O Specifications ............................................................................................................................. 4
DC Specifications........................................................................................................................................ 5
AC Specifications ........................................................................................................................................ 6
Input Timing Diagrams ................................................................................................................................ 7
Pin Descriptions.............................................................................................................................................. 9
Input Pins .................................................................................................................................................... 9
Configuration Pins..................................................................................................................................... 10
Input Voltage Reference Pin ..................................................................................................................... 11
Power Management Pins.......................................................................................................................... 11
Differential Signal Data Pins ..................................................................................................................... 11
Reserved Pins........................................................................................................................................... 11
Power and Ground Pins............................................................................................................................ 11
2
I C Registers................................................................................................................................................. 12
I
2
C Register Mapping ................................................................................................................................ 12
I
2
C Register Definitions ............................................................................................................................. 13
I
2
C Slave Interface and Address ............................................................................................................... 15
Data De-skew Feature .............................................................................................................................. 16
Data Latching Modes ................................................................................................................................ 17
I
2
C Programming Sequence ..................................................................................................................... 18
Enabling Hot Plug Detection Mode........................................................................................................... 18
Non-I
2
C/Strap Mode Configuration ........................................................................................................... 19
TFT Panel Data Mapping.............................................................................................................................. 21
Design Recommendations ........................................................................................................................... 24
1.5V to 3.3V I
2
C Bus Level-Shifting .......................................................................................................... 24
Voltage Ripple Regulation......................................................................................................................... 25
Decoupling Capacitors.............................................................................................................................. 26
Series Damping Resistors on Outputs...................................................................................................... 27
Differential Trace Routing ......................................................................................................................... 27
Package Dimensions and Marking Specification ......................................................................................... 29
Ordering Information..................................................................................................................................... 29
iii
SiI-DS-0021-E
SiI
164 PanelLink Transmitter
Data Sheet
LIST OF TABLES
Table 1. Data De-Skew Estimated Values .................................................................................................... 16
Table 2. Sample Programming Sequence for
SiI
164 in 12-bit Mode .......................................................... 18
Table 3. Non-I
2
C/Strap Mode Options .......................................................................................................... 20
Table 4. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 Compliant.............................. 21
Table 5. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode................................ 22
Table 6. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode................................ 23
Table 7. Recommended Components for Bypass and Decoupling Circuits................................................. 26
LIST OF FIGURES
Figure 1. Pin Diagram for
SiI
164 ................................................................................................................... 1
Figure 2. Functional Block Diagram ............................................................................................................... 2
Figure 3. Clock Cycle High/Low Times........................................................................................................... 7
Figure 4. Low Swing Differential Times .......................................................................................................... 7
Figure 5. ISEL/RST# Minimum Timing ........................................................................................................... 7
Figure 6. Input Data Setup/Hold Time to IDCK .............................................................................................. 8
Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE ...................................................................... 8
Figure 8. DE High and Low Times.................................................................................................................. 8
Figure 9. I
2
C Data Valid Delay (driving Read Cycle data) .............................................................................. 8
Figure 10. I
2
C Byte Read.............................................................................................................................. 15
Figure 11. I
2
C Byte Write .............................................................................................................................. 15
Figure 12.
SiI
164 Data De-skew Feature Timing ........................................................................................ 16
Figure 13. 12-bit Input Data Latching ........................................................................................................... 17
Figure 14. 24-bit Input Data Latching ........................................................................................................... 17
Figure 15. Non- I
2
C/Strap Mode Schematic Example .................................................................................. 19
Figure 16. I
2
C Bus Voltage Level-Shifting using Fairchild NDC7002N ........................................................ 24
Figure 17. I
2
C Bus Voltage Level Shifting using Philips GTL 2010 .............................................................. 24
Figure 18. Voltage Regulation using TL431 ................................................................................................. 25
Figure 19. Voltage Regulation using LM317 ................................................................................................ 25
Figure 20. Decoupling and Bypass Capacitor Placement............................................................................ 26
Figure 21. Decoupling and Bypass Schematic............................................................................................. 26
Figure 22. Series Input Damping Resistors for Driving Source ................................................................... 27
Figure 23. Example of Incorrect Differential Signal Routing ........................................................................ 27
Figure 24. Example of Correct Differential Signal Routing........................................................................... 28
Figure 25. Differential Trace Routing to DVI Connector(Top Side View) ..................................................... 28
Figure 26. 64-pin TQFP Package Dimensions (JEDEC code MS-026ACD) ............................................... 29
SiI-DS-0021-E
iv
SiI
164 PanelLink Transmitter
Data Sheet
September 2002
General Description
The
SiI
164 transmitter uses PanelLink
®
Digital
technology to support displays ranging from VGA to
UXGA resolutions (25 - 165Mpps) in a single link
interface.
The
SiI
164 transmitter has a highly flexible interface
with either a 12-bit mode (½ pixel per clock edge) or
24-bit mode 1 pixel per clock edge input for true color
(16.7 million) support. In 24-bit mode, the
SiI
164
supports single or dual edge clocking. In 12-bit mode,
the SiI164 supports dual edge single clocking or
single edge dual clocking. The
SiI
164 can be
programmed though an I
2
C interface. In addition the
SiI
164 also supports Receiver and Hot Plug
Detection.
PanelLink Digital technology simplifies PC design by
resolving many of the system level issues associated
with high-speed mixed signal design, providing the
system designer with a digital interface solution that
is quicker to market and lower in cost.
Features
•
•
•
•
•
•
•
•
•
•
•
Scaleable Bandwidth: 25 - 165MHz Flexible
Graphics Controller Interface: 12-bit or 24-bit
mode 1 pixel/clock inputs
Flexible Input Clocking: Single clock single
edge (24-bit), Single clock dual edge (12-/24-
bit), Dual clock single edge (12-bit)
I
2
C Slave Programming Interface up to 100kHz
Low Voltage Interface: 3.3V with option for 1.0
to 3.0V Low Voltage Signal Mode
Monitor Detection supported through hot plug
and receiver detection
De-skewing Option varies input clock to input
data timing
Low Power: 3.3V operation (120mA max.) and
Power Down mode (1mA max.)
Cable Distance Support: over 5m with twisted
pair and fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards
compliant with VESA
®
P&D
TM
and DFP)
Standard and Pb-free packages (see pg 29)
SiI
164 Pin Diagram
EXT_SWING
PVCC1
18
AGND
AGND
AGND
PGND
17
16
15
14
13
12
11
AVCC
AVCC
TXC+
22
TX2+
TX1+
TX0+
TXC-
21
TX2-
TX1-
TX0-
24
32
31
30
29
28
27
26
25
23
20
19
VCC
RESERVED
DKEN
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
GND
33
GND
BSEL/SCL
DSEL/SDA
ISEL/RST#
VCC
MSEN
PD#
EDGE/HTPLG
CTL1/A1/DK1
CTL2/A2/DK2
CTL3/A3/DK3
VSYNC
HSYNC
VREF
DE
VCC
34
35
36
37
38
39
40
41
42
43
44
45
46
47
54
58
62
50
51
52
53
55
56
57
59
60
49
61
63
SiI
164
64-Pin TQFP
(Top View)
10
9
8
7
6
5
4
3
2
64
GND
1
48
IDCK+
D9
D8
D7
D6
D5
D4
D3
D2
D1
D11
PVCC2
D10
Figure 1. Pin Diagram for
SiI
164
IDCK-
D0
1
SiI-DS-0021-E
模拟电子
