®
Technology
SiI 178
PanelLink Transmitter
Data Sheet
Document # SiI-DS-0086-D
SiI 178
PanelLink Transmitter
Data Sheet
Silicon Image, Inc.
SiI-DS-0086-D
March 2004
Application Information
To obtain the most updated Application Notes and other useful information for your design, contact your local
Silicon Image sales office. Please also visit the Silicon Image web site at
www.siliconimage.com.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
is a registered trademark of the Video
Electronics Standards Association. All other trademarks are the property of their respective holders.
Trademark Acknowledgment
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
Revision History
Revision
A
B
Date
7/18/2002
11/8/2002
Comment
Release to Production with complete parametric information.
Added 12-bit Setup and Hold numbers, De-skew range, Dual Link application, ESD
guidelines, MSJL register setting and Design Guidelines. DK1 and DK2 control info.
Changed EDGE/CHG to EDGE/HTPLG. Added Pb-free package.
Updated Deskew pin definition from pin 7 =DK1/DK2 to pin 7 = NC and pin 8 = NC to
pin 8 =DK1. Updated Deskew timing table.
Added Slave Tx I C addressing mode in Power Down mode after Reset. PD# bit renamed
correctly to PD. Replaced LM317 with LM1117-3.3V. Corrected “D1” & “c” dimensions &
added max dimension on “b” on page on page 36. Changed default DK3..1] bit setting after
RESET.
2
C
D
1/22/2003
3/10/2004
© 2004 Silicon Image
ii
SiI-DS-0086-D
SiI 178
PanelLink Transmitter
Data Sheet
TABLE OF CONTENTS
Functional Description .................................................................................................................................... 2
PanelLink TMDS Core ................................................................................................................................ 2
I
2
C Interface and Registers......................................................................................................................... 2
Data Capture Logic ..................................................................................................................................... 3
Electrical Specifications .................................................................................................................................. 4
Absolute Maximum Conditions ................................................................................................................... 4
Normal Operating Conditions ..................................................................................................................... 4
DC Specifications........................................................................................................................................ 5
AC Specifications ........................................................................................................................................ 6
Timing Diagrams ......................................................................................................................................... 7
Pin Descriptions............................................................................................................................................ 10
Input Pins .................................................................................................................................................. 10
Input Voltage Reference Pin ..................................................................................................................... 10
Power Management Pin............................................................................................................................ 11
Differential Signal Data Pins ..................................................................................................................... 11
Power and Ground Pins............................................................................................................................ 11
Dual Link Configuration and Control Pins................................................................................................. 12
Feature Information ...................................................................................................................................... 14
DDC / I
2
C Interface ................................................................................................................................... 14
Data De-skew Feature .............................................................................................................................. 15
Reset Requirements ................................................................................................................................. 16
Chip State After Reset ........................................................................................................................... 16
Dual Link Mode............................................................................................................................................. 17
Dual Link Configuration............................................................................................................................. 18
Master ....................................................................................................................................................... 18
Slave ......................................................................................................................................................... 18
I
2
C ............................................................................................................................................................. 18
Timing Diagrams ....................................................................................................................................... 19
TFT Panel Data Mapping.............................................................................................................................. 20
Data Mapping for Dual Link 12-bit Mode............................................................................................... 23
Data Latching Modes ................................................................................................................................ 24
Register Maps ........................................................................................................................................... 25
Base Register Set ................................................................................................................................. 25
Register Initialization................................................................................................................................. 28
Design Recommendations ........................................................................................................................... 29
1.5V to 3.3V I
2
C Bus Level-Shifting .......................................................................................................... 29
ESD Protection on TMDS Output Pins ..................................................................................................... 30
Voltage Ripple Regulation......................................................................................................................... 31
PCB Ground Planes.................................................................................................................................. 32
Decoupling Capacitors.............................................................................................................................. 32
Series Damping Resistors on Inputs ........................................................................................................ 33
Transmitter Layout .................................................................................................................................... 33
Recommended Circuits............................................................................................................................. 35
Packaging ..................................................................................................................................................... 36
Ordering Information..................................................................................................................................... 36
SiI-DS-0086-D
iii
SiI 178
PanelLink Transmitter
Data Sheet
LIST OF TABLES
Table 1. De-Skew Register Estimated Values .............................................................................................. 15
Table 2. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 Compliant.............................. 20
Table 3. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode................................ 21
Table 4. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode................................ 22
Table 5. Dual Link Data Mapping.................................................................................................................. 23
Table 6. Base Register Set ........................................................................................................................... 25
Table 7. I
2
C Register Definitions................................................................................................................... 26
Table 8. Recommended Components .......................................................................................................... 32
Table 9. DVI Connector to
SiI
178 for Dual Link Pin Connection ................................................................. 34
LIST OF FIGURES
Figure 1.
SiI
178 Pin Diagram ........................................................................................................................ 1
Figure 2. Functional Block Diagram ............................................................................................................... 2
Figure 3. Clock Cycle/High/Low Times........................................................................................................... 7
Figure 4. Control and 24-bit Single-Edge-Data Setup/Hold Times to IDCK+/IDCK-...................................... 7
Figure 5. 12-bit/24-bit Dual Edge Data Setup/Hold Times to IDCK+ ............................................................. 7
Figure 6. VSYNC, HSYNC and CTL3 Delay Times from/to DE ..................................................................... 8
Figure 7. DE High/Low Times......................................................................................................................... 8
Figure 8. RESET (ISEL/RST#) Minimum Timings.......................................................................................... 8
Figure 9. Differential Transition Times ............................................................................................................ 9
Figure 10. I
2
C Data Valid Delay (Driving Read Cycle Data)........................................................................... 9
Figure 11. I
2
C Byte Read .............................................................................................................................. 14
Figure 12. I
2
C Byte Write .............................................................................................................................. 14
Figure 13. De-skewing Feature Timing ........................................................................................................ 15
Figure 14. Dual Link Configuration............................................................................................................... 17
Figure 15. Single/Dual Link Timing Diagram ................................................................................................ 19
Figure 16. 12-bit Input Data Latching ........................................................................................................... 24
Figure 17. 24-bit Input Data Latching ........................................................................................................... 24
Figure 18. I
2
C Bus Voltage Level-Shifting using Fairchild NDC7002N ........................................................ 29
Figure 19. I
2
C Bus Voltage Level Shifting using Philips GTL 2010 .............................................................. 29
Figure 20. ESD Protection Circuit ................................................................................................................ 30
Figure 21. Voltage Regulation using TL431 ................................................................................................. 31
Figure 22. Voltage Regulation using LM1117-3.3V ...................................................................................... 31
Figure 23. Decoupling and Bypass Capacitor Placement............................................................................ 32
Figure 24. Decoupling and Bypass Schematic............................................................................................. 32
Figure 25. Transmitter Input Series Damping Resistors .............................................................................. 33
Figure 26. Transmitter to DVI Connector Layout.......................................................................................... 33
Figure 27. Recommended Hot Plug Connection.......................................................................................... 35
Figure 28. Package Diagram........................................................................................................................ 36
iv
SiI-DS-0086-D
SiI
178 PanelLink Transmitter
Data Sheet
March 2004
General Description
The SiI 178 transmitter uses PanelLink Digital
technology to support displays ranging from
VGA to UXGA resolution (25 - 165Mpps) in a
single link interface. With two
SiI
178 devices,
dual link resolutions of up to QUXGA(330Mpps)
can be achieved.
The SiI 178 is pin compatible with the SiI 168,
supporting either a 12-bit mode (½ pixel per
clock edge) or 24-bit mode (1-pixel per clock
edge) for true color (16.7 million) support. In 24-
bit mode, the SiI 178 supports single or dual
edge clocking. In 12-bit mode, the SiI 178
supports dual edge single clock or single edge
dual clock. The SiI 178 can be programmed
though an I
2
C interface.
PanelLink Digital technology simplifies PC
design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a
digital interface solution that is quicker to
market and lower in cost.
•
•
•
Features
Scaleable Bandwidth: 25 - 165 Mega-pixels
per second (VGA to UXGA)
Supports Dual-Link operation up to 330
Mega-pixels per second
Flexible Graphics Controller Interface: 12-bit
(½ pixel) or 24-bit mode 1 pixel per clock
input
Flexible Input Clocking: Single clock single
edge (24-bit), Single clock dual edge (12-
/24-bit), Dual clock single edge (12-bit)
I
2
C Slave Programming Interface
Low Voltage Interface: 3.3V with option for
1.0 to 1.8V
Monitor Detection supported through hot
plug and receiver detection
Cable Distance Support: over 5m with
twisted pair and fiber-optics ready
Compliant with DVI 1.0
Standard and Pb-free packages (see page
36).
•
•
•
•
•
•
•
SiI 178
Pin Diagram
EXT_SWING
AGND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VC C
R ESERVED
G ND
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14/SYN CO
D13/M AST
D 12/DU AL
PG ND 2
18
17
PGND1
PVCC1
AGND
AGND
AVCC
AVCC
TXC+
TX2+
TX1+
TX0+
TXC-
TX2-
TX1-
TX0-
33
16
GND
B SEL/SC L
D SEL/SDA
ISEL/R ST#
V CC
M SEN
P D#
E DG E/H TPLG
DK1
NC
D K3
V SYN C
H SYN C/SYN CI
V REF
DE
VCC
34
35
36
37
38
39
40
41
42
43
44
45
46
47
54
58
50
51
52
53
55
56
57
59
60
61
62
63
49
15
14
13
12
11
SiI
178
64-Pin TQ FP
(Top View )
10
9
8
7
6
5
4
3
2
64
1
48
PVCC2
IDCK+
IDCK-
Figure 1.
SiI
178 Pin Diagram
SiI-DS-0086-D
1
GND
D8
D9
D7
D6
D5
D4
D3
D2
D1
D11
D10
D0
