SiI2022 SerDes
Data Sheet
General Description
Silicon Image’s SiI2022 is a serializer/deserializer
(SerDes) capable of transmitting and receiving data at
1.0625 and 2.125 gigabits-per-second (Gbps) targeting
Fibre Channel applications. Designed for power,
performance and price, the SiI2022 SerDes makes use of
a robust, low-power, low-cost, low-jitter, CMOS design that
comes in compact 64-pin, 14 mm MQFP package. The
Sil2022 supports selectable transmit and receive data
rates for automatic speed negotiation and a narrow 10-bit
SSTL_2 compatible interface for parallel data input/output.
The innovative PLL design enables high data reliability
and ease-of-design while eliminating the need for external
PLL capacitors.
The SiI2022 leverages much of the circuit innovation at the
physical layer of Silicon Image’s proprietary reduced
overhead Multi-layer Serial Link (MSL
TM
) architecture,
which was pioneered and proven with our market-leading
PanelLink products. Silicon Image has shipped over 25
million units of PanelLink products for host systems and
displays in the PC and the CE markets, notable for their
noisy operating conditions. The MSL technology is a
multi-layered approach to providing cost-effective, multi-
gigabit semiconductor solutions on a single chip for high-
bandwidth applications.
Features
April 2002
General
•
Fibre Channel-compliant
•
Multi-rate: 1.0625 Gbps and 2.125 Gbps
Low Power
•
Single 3.3V supply for core circuits and high-speed
•
I/O
Power dissipation at 2.125 Gbps: 446 mW (typical)
Cost Effective
•
Standard CMOS technology
•
Compact 64-pin, 14 x 14mm MQFP package
Narrow parallel I/O Interface
•
10-bit interface with DDR for 2.125 Gbps mode
•
SSTL_2 and High-Speed Parallel Interface (HSPI)-
•
compliant
Separate transmit byte clock (TBC) for latching
parallel input data
Highly Reliable Serial Interface
•
Separately selectable Tx and Rx data rates
•
Low-jitter PLL : 3.5 ps (random jitter), 32 ps
•
•
(deterministic jitter)
Pre-emphasis control
On-chip termination resistor
Figure 1. SiI2022 Pin Diagram
GN D _TXH S
R X_R ATE
GN D _R XA
Vcc_TXH S
Vcc_TXH S
Vcc_R XA
Vcc_R XA
EQAMP
Proven Technology
•
MSL-based technology proven with PanelLink
•
ICs for the PC and the CE markets (2-5 Gbps, over
25M units shipped)
Robust design for “noisy” environments
SO +
GN D
SO -
SI +
Vcc
Vcc
Vcc
53
64
63
62
61
60
59
58
57
56
55
54
SI -
52
51
50
49
48
47
46
45
44
43
TBC
TX[0 ]
TX[1 ]
TX[2 ]
VR EFT
TX[3 ]
TX[4 ]
TX[5 ]
TX[6 ]
R BC _ SYN C
TX[7 ]
TX[8 ]
TX[9 ]
TX_ R ATE
GN D _ TXA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VR EFR
GN D _ SSTL
R X[0 ]
R X[1 ]
R X[2 ]
Vcc_ SSTL
R X[3 ]
R X[4 ]
R X[5 ]
R X[6 ]
Vcc_ SSTL
R X[7 ]
R X[8 ]
R X[9 ]
GN D _ SSTL
SiI2022
64-p in
M QF P
42
41
40
39
38
37
36
35
34
33
R BC [1]
Vcc_TXA
Vcc_TXA
R EF_R ATE
R EFC LK[1]
R EFC LK[0]
C OM_D ET
EN _C D ET
EWR AP
R X_LOS
R BC [0]
Vcc
Vcc
Preliminary Data Sheet
GN D _SSTL
GN D
GN D
1
Subject to Change without Notice
SiI2022
Functional Block Diagram
TX[0:9]
Input
Latch
Serializer
Serial
Output
Driver
SO ±
1.0625/2.125Gbps
Transmit signal
TBC
TX_RATE
REFCLK[0:1]
RX_RATE
RBC[0:1]
TX PLL
Loopback
RX PLL
RBC_SYNC
RX[0:9]
EN_CDET
Parallel
Output
Driver
Byte
Sync
Deserializer
Input
Sampler
1.0625/2.125 Gbps
receive signal
SI ±
COM_DET
EWRAP
Figure 2. Functional Block Diagram
SiI2022 Block Diagram
The SiI2022 (Figure 2) is designed to transmit and receive 10-bit wide parallel data over high-speed serial
communication lines. The parallel data applied to the transmitter is expected to be encoded per the 8B/10B encoding
scheme with special reserved characters for link management purposes. The SiI2022 incorporates the following:
• SSTL_2 Parallel I/O
• High Speed Phase Locked Loops
• Parallel to Serial Converter
• High Speed Serial Clock and Data Recovery Circuitry
• Comma Character Recognition per Fibre Channel Specifications
• Byte Alignment Circuitry
• Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide single ended SSTL_2 parallel data at inputs TX[0:9]. The SSTL_2 TBC clock
provided by the sender of the transmit data is used as the transmit byte clock. The TX[0:9] and TBC signals must be
properly aligned as shown in Figure 3. If TX_RATE = 1, TX[0:9] data are latched between both edges of TBC.
If TX_RATE = 0, TX[0:9] data are latched on the falling edge of TBC. The TX[0:9] and TBC inputs are
unterminated SSTL_2 inputs.
TX PLL/CLOCK GENERATOR
The Transmitter Phase Locked Loop and Clock Generator block is responsible for generating all internal clocks
needed by the transmitter section to perform its functions. These clocks are based on the supplied transmit byte
clock (TBC). Incoming data must be synchronous with TBC.
Preliminary Data Sheet
2
Subject to Change without Notice
SiI2022
SERIALIZER
The SERIALIZER accepts 10-bit wide parallel data from the INPUT LATCH. Using internally generated high-
speed clocks, this parallel data is multiplexed into a 2.125 Gbps serial data stream. The data bits are transmitted
sequentially from TX[0] to TX[9]. The leftmost bit of K28.5+ is on TX[0].
SERIAL OUTPUT DRIVER
The SERIAL OUTPUT DRIVER block drives the serial data to the serial output line. In normal operation, the
serialized TX[0:9] data is placed at SO± . In parallel loopback (EWRAP=1) mode, the SO± pins are held static at
logic 1. In addition, the SERIAL OUTPUT DRIVER block allows the user to control the amount of pre-emphasis
used on the SO± pins. If pre-emphasis is used, 0 to 1 and 1 to 0 transitions on SO± have greater amplitude than 0 to
0 and 1 to 1 transitions. This increased amplitude is used to offset the effects of skin loss and dispersion on long
PCB transmission lines. Pre-emphasis is controlled by the EQAMP pin.
RX PLL/CLOCK RECOVERY
The Receiver Phase Locked Loop and Clock Recovery block is responsible for frequency and phase locking onto
the incoming serial data stream and recovering the bit and byte clocks. An automatic locking feature allows the Rx
PLL to lock onto the input data stream without external PLL training controls. It does this by continually frequency
locking onto the 106.25 MHz reference clock, and then phase locking onto the selected input data stream. An
internal circuitry monitors the frequency of RX PLL and invokes the phase detection as the frequency is locked.
INPUT SAMPLER
The INPUT SAMPLER is responsible for converting the serial input signal into a retimed bit stream. To accomplish
this, it uses the high-speed serial clock generated from the RX PLL/CLOCK RECOVERY block. This serial bit
stream is sent to the DESERIALIZER block.
DESERIALIZER
The DESERIALIZER block is responsible for converting the serial data from INPUT SAMPLER to parallel data.
BYTE SYNC
The BYTE SYNC block is responsible for recognizing the first seven bits of the K28.5+ positive disparity comma
character (0011111xxx). When recognized, the BYTE SYNC block works with the RX PLL/CLOCK RECOVERY
block to select the proper parallel data edge out of the bit stream so that the next comma character starts at RX[0].
When a comma character is detected and realignment of the receive byte clock RBC[0:1] is necessary, these clocks
are stretched (never slivered) to the next correct alignment position. RBC[0:1] will be aligned by the start of the
next ordered set (four-byte group) after K28.5+ is detected. The start of the next ordered set will be aligned with the
rising edge of RBC[1], independent of the RX_RATE pin setting. Per the Fibre Channel encoding scheme, comma
characters must not be transmitted in consecutive bytes so that the receive byte clocks may maintain their proper
recovered frequencies.
PARALLEL OUTPUT DRIVER
The PARALLEL OUTPUT DRIVERS present the 10-bit parallel recovered data (RX[0:9]) properly aligned to the
receive byte clock (RBC[0:1]) as shown in Figures 5. These output drivers provide single ended SSTL_2
compatible signals.
Preliminary Data Sheet
3
Subject to Change without Notice
SiI2022
Electrical Specifications
Absolute Maximum Conditions
Symbol
Description
Min
Typ
Max
Units
V
CC
Supply Voltage 3.3V
-0.5
4.0
V
V
I
Input Voltage
-0.3
V
CC
+ 0.3
V
T
J
Junction Temperature (with power applied)
125
°C
T
STG
Storage Temperature
-65
150
°C
Thermal Resistance (Junction to Ambient)
33
°C/W
θ
JA
Notes: Permanent device damage may occur if absolute maximum conditions are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions below.
Normal Operating Conditions
Symbol
Description
V
CC
Supply Voltage
T
A
Ambient Temperature (with power applied)
Min
3.15
0
Typ
3.3
25
Max
3.45
70
Units
V
°C
DC Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
V
DDQ
=2.30V to 2.70V. V
DDQ
is the FC-1/MAC device I/O supply voltage.
Symbol Parameter
Min
VREFT Input reference voltage
1.15
V
IH
V
IL
V
IHPECL
V
ILPECL
V
IHLVTTL
V
ILLVTTL
VREFR
V
OH
V
OL
High level input Voltage
Low level input Voltage
High level LVPECL input Voltage for
REFCLK[0:1]
Low level LVPECL input Voltage for
REFCLK[0:1]
High level LVTTL input Voltage for
REFCLK[0:1]
Low level LVTTL input Voltage for
REFCLK[0:1]
Output reference voltage
High level output voltage
Low level output voltage
1.15
VREFR+0.38
GND
VREFT+0.35
-0.30
2.10
1.30
2.0
Typ
1.25
Max
1.35
V
DDQ
+0.30
VREFT-
0.35V
2.60
1.80
Units
V
V
V
V
V
V
0.80
1.25
1.35
V
DDQ
VREFR-0.43
V
V
V
V
Preliminary Data Sheet
4
Subject to Change without Notice
SiI2022
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter
Conditions
V
SOUT75
SO+/SO- differential peak- Terminated by
to-peak voltage swing.
75 Ohms
V
SOUT50
V
IN
V
DIH
V
DOH
SO+/SO- differential peak-
to-peak voltage swing.
SI+/SI- differential peak-to-
peak input sensitivity
SI+/SI- differential Input
common-mode voltage
[3]
SO+/SO-differential Output
common-mode voltage
[3]
Power dissipation
C
LOAD
=5pF
2.125 Gbps rate
TX+/- = 50ohms
terminated
Terminated by
50 Ohms.
Min
1100
800
200
Typ
1400
1050
Max
2000
2000
2000
Units
mV
mV
mV
V
V
1.65
2.78
P
CC
446
[1]
680
[2]
mW
[1] Sending/Receiving Random Pattern
[2] Sending/Receiving Worst Case (maximum transitions) Pattern
[3] Self biased
REFCLK[0:1], TBC Parameters
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
T
REF_FREQ
Nominal Frequency
T
REF_J
T
REF_DUTY
REFCLK[0:1] frequency tolerance
REFCLK[0:1] duty cycle
Min
-200
40%
Typ
106.25
Max
200
60%
Units
MHz
ppm
Transmit Function AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
T
TXS
TX[0:9] setup time to the falling edge of TBC
(TX_RATE=0)
T
TXH
T
TCT
T
TCV
T
RISE
T
FALL
T
TXLAT
TX[0:9] hold time from the falling edge of TBC
(TX_RATE=0)
TX[0:9], TBC transition time (TX_RATE=1)
TX[0:9], TBC valid/stable time (TX_RATE=1)
SO+/SO- rise time into 50 Ohms. Measured from
20% and 80% of full swing.
SO+/SO- fall time into 50 Ohms. Measured from
20% and 80% of full swing.
Latency from TX[0:9] parallel input to SO+/SO-
serial output
Min
1400
1400
Typ
Max
Units
ps
ps
1880
2820
160
160
0.4+10
ps
ps
ps
ps
ns..bit
Preliminary Data Sheet
5
Subject to Change without Notice
工控电子
