SII8788CNUC,SII8788CNUC pdf中文资料,SII8788CNUC引脚图,SII8788CNUC电路-Datasheet-电子工程世界

文档预览

SiI8788 Analog Front-end Video Processor

with Parallel Video Output

Data Sheet

SiI-DS-1123-A

March 2016

SiI8788 Analog Front-end Video Processor with Parallel Video Output

Data Sheet

Contents

General Description ......................................................................................................................................................5

1.1. Features ................................................................................................................................................................5

1.1.1.

Analog (Video) Front-end..............................................................................................................................5

1.1.2.

Multi-format Video Decoder .........................................................................................................................5

1.1.3.

Video Processing ...........................................................................................................................................5

1.1.4.

24-bit Parallel Output ...................................................................................................................................5

1.2. Applications ..........................................................................................................................................................5

1.3. Packaging ..............................................................................................................................................................5

1.4. Temperature Range ..............................................................................................................................................5

2. Product Family ..............................................................................................................................................................6

3. Functional Description ..................................................................................................................................................7

3.1. Analog Front-end ..................................................................................................................................................8

3.1.1.

Input Multiplexer ..........................................................................................................................................8

3.1.2.

Clamp and Offset ..........................................................................................................................................8

3.1.3.

Low Pass Filter...............................................................................................................................................8

3.1.4.

ADC with Programmable Gain Amplifier.......................................................................................................8

3.1.5.

Line Locked PLL .............................................................................................................................................9

3.1.6.

Sync Slicer .....................................................................................................................................................9

3.1.7.

Video Buffer ..................................................................................................................................................9

3.2. Video Decoder ......................................................................................................................................................9

3.2.1.

ADCIF ...........................................................................................................................................................10

3.2.2.

Automatic Gain Control and Offset Calibration ..........................................................................................10

3.2.3.

Antialias Filtering and Decimation ..............................................................................................................10

3.2.4.

Video Decoder ............................................................................................................................................10

3.2.5.

CVBS Processing ..........................................................................................................................................10

3.2.6.

Component Processing ...............................................................................................................................11

3.2.7.

Sync Processor ............................................................................................................................................11

3.2.8.

VBI Decoder ................................................................................................................................................11

3.3. Video Processing .................................................................................................................................................12

3.3.1.

Time Base Corrector ...................................................................................................................................12

3.3.2.

VBI Post Processor ......................................................................................................................................12

3.3.3.

De-interlacer and Edge Smoother...............................................................................................................12

3.3.4.

Color Processing ..........................................................................................................................................12

3.3.5.

Auto Phase Detection .................................................................................................................................13

3.3.6.

Auto Position Calibration ............................................................................................................................13

3.3.7.

Auto Gain Calibration ..................................................................................................................................13

3.4. Video Path ...........................................................................................................................................................13

3.4.1.

Video Data Conversion Logic Block .............................................................................................................13

3.4.2.

Digital Parallel Video Output Interface .......................................................................................................14

3.5. Control Logic .......................................................................................................................................................15

3.5.1.

Internal Microcontroller .............................................................................................................................15

3.5.2.

Registers......................................................................................................................................................17

3.5.3.

I C Bus .........................................................................................................................................................17

3.5.4.

Interrupt......................................................................................................................................................18

3.5.5.

GPIOs...........................................................................................................................................................18

4. Electrical Specifications ..............................................................................................................................................19

4.1. Absolute Maximum Ratings ................................................................................................................................19

4.2. Normal Operating Conditions .............................................................................................................................20

4.3. ESD Specifications ...............................................................................................................................................20

4.4. DC Specifications .................................................................................................................................................21

4.5. AC Specifications .................................................................................................................................................22

4.6. Control Signal Timing Specifications ...................................................................................................................23

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1123-A

SiI8788 Analog Front-end Video Processor with Parallel Video Output

Data Sheet

Timing Diagrams ......................................................................................................................................................... 24

5.1. I C Bus Timing Diagrams ..................................................................................................................................... 24

5.2. Reset Timing Diagram ......................................................................................................................................... 24

5.3. Digital Video Output Timing Diagrams ............................................................................................................... 25

6. Pin Diagram and Pin Description ................................................................................................................................ 26

6.1. Pin Diagram......................................................................................................................................................... 26

6.2. Pin Descriptions .................................................................................................................................................. 27

6.2.1.

AFE Input/Output Pins ................................................................................................................................ 27

6.2.2.

Configuration and Control Pins ................................................................................................................... 28

6.2.3.

Parallel Video Output Data Pins .................................................................................................................. 29

6.2.4.

SPI Interface Pins ........................................................................................................................................ 30

6.2.5.

Power and Ground Connections ................................................................................................................. 30

6.2.6.

Crystal Pins .................................................................................................................................................. 30

6.2.7.

Reserved Pins .............................................................................................................................................. 31

6.2.8.

Output Pin Mappings .................................................................................................................................. 31

7. Design Guidelines ....................................................................................................................................................... 37

7.1. Power Supplies Decoupling ................................................................................................................................ 37

7.2. ESD Protection .................................................................................................................................................... 38

7.3. EMI Considerations ............................................................................................................................................. 38

7.4. Typical Circuit Connection .................................................................................................................................. 38

8. Packaging .................................................................................................................................................................... 39

8.1. ePad Requirements............................................................................................................................................. 39

8.2. Package Dimensions ........................................................................................................................................... 40

9. Marking Specification ................................................................................................................................................. 41

9.1. Ordering Information .......................................................................................................................................... 41

References .......................................................................................................................................................................... 42

Standards Documents..................................................................................................................................................... 42

Lattice Semiconductor Documents ................................................................................................................................. 42

Revision History .................................................................................................................................................................. 43

Figures

Figure 1.1. Typical Application of the SiI8788 Device ........................................................................................................... 5

Figure 3.1. Functional Block Diagram ................................................................................................................................... 7

Figure 3.2. Clamp and Offset ................................................................................................................................................ 8

Figure 3.3. Sync Slicers.......................................................................................................................................................... 9

Figure 3.4. CVBS Processing Diagram ................................................................................................................................. 10

Figure 3.5. Component Processing Diagram....................................................................................................................... 11

Figure 3.6. Default Video Processing Path .......................................................................................................................... 13

Figure 3.7. External Memory Structure .............................................................................................................................. 16

Figure 5.1. I C Data Valid Delay (Driving Read Cycle Data) ................................................................................................. 24

Figure 5.2. Conditions for Use of RESET_N ......................................................................................................................... 24

Figure 5.3. RESET_N Minimum Timings .............................................................................................................................. 24

Figure 5.4. Video Digital Output Transition Times .............................................................................................................. 25

Figure 5.5. Clock-to-Output Delay and Duty Cycle Limits ................................................................................................... 25

Figure 6.1. Pin Diagram....................................................................................................................................................... 26

Figure 7.1. Decoupling and Bypass Schematic .................................................................................................................... 37

Figure 7.2. Decoupling and Bypass Capacitor Placement ................................................................................................... 37

Figure 7.3. Typical Circuit Schematic .................................................................................................................................. 38

Figure 8.1. 88-Pin QFN Package Diagram ........................................................................................................................... 40

Figure 9.1. Marking Diagram .............................................................................................................................................. 41

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1123-A

SiI8788 Analog Front-end Video Processor with Parallel Video Output

Data Sheet

Tables

Table 2.1. Product Selection Guide.......................................................................................................................................6

Table 3.1. Supported Standards..........................................................................................................................................12

Table 3.2. Typical Digital Video Output Formats ................................................................................................................15

Table 3.3. Head Flags ..........................................................................................................................................................16

Table 3.4. Info Bytes ...........................................................................................................................................................16

Table 3.5. SPI Parameter .....................................................................................................................................................17

Table 3.6. Calibration Checksum ........................................................................................................................................17

Table 3.7. HW Configuration Data ......................................................................................................................................17

Table 3.8. 8051 Code Size ...................................................................................................................................................17

Table 3.9. HW Configuration Data and Code Checksum.....................................................................................................17

Table 3.10. Control of Transmitter I C Address with CI2CA Signal .....................................................................................18

Table 3.11. GPIOs ................................................................................................................................................................18

Table 4.1. Absolute Maximum Ratings ...............................................................................................................................19

Table 4.2. Normal Operating Conditions ............................................................................................................................20

Table 4.3. ESD Specifications ..............................................................................................................................................20

Table 4.4. Digital I/O Specifications ....................................................................................................................................21

Table 4.5. Analog Front-end Electrical Specifications .........................................................................................................22

Table 4.6. Parallel Video Output Timing Specifications ......................................................................................................23

Table 4.7. Control Signal Timing Specifications ..................................................................................................................23

Table 6.1. AFE Input/Output Pins .......................................................................................................................................27

Table 6.2. Configuration and Control Pins ..........................................................................................................................28

Table 6.3. Parallel RGB Output Data Pins ...........................................................................................................................29

Table 6.4. SPI Interface Pins ................................................................................................................................................30

Table 6.5. Power and Ground Connections ........................................................................................................................30

Table 6.6. Crystal Pins .........................................................................................................................................................30

Table 6.7. Reserved Pins .....................................................................................................................................................31

Table 6.8. RGB/YCbCr 4:4:4 Separate Sync Data Mapping .................................................................................................31

Table 6.9. YCbCr 4:2:2 Separate Sync Data Mapping..........................................................................................................32

Table 6.10. YCbCr 4:2:2 Embedded Sync Data Mapping.....................................................................................................33

Table 6.11. YCbCr Mux 4:2:2 Separate Sync Data Mapping ...............................................................................................34

Table 6.12. YCbCr Mux 4:2:2 Embedded Sync Data Mapping ............................................................................................35

Table 6.13. 12-bit RGB and YCbCr 4:4:4 Separate Sync Data Mapping ..............................................................................36

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1123-A

SiI8788 Analog Front-end Video Processor with Parallel Video Output

Data Sheet

1. General Description

The Lattice Semiconductor SiI8788 processor is a high

quality Analog Front-end (AFE) and multistandard

composite or component Video Decoder (VDC). A

microcontroller is integrated to reduce the system

BOM cost.

The SiI8788 processor supports worldwide PAL, NTSC

and SECAM standards, YP

video signals up to

1080p @ 60 Hz resolution.

The device contains a Time Base Correction (TBC)

module, a de-interlacer with a post-processor engine

and a VBI decoder.

1.1.3. Video Processing



Time Base Correction

De-interlacer with Edge Smoothing

Automatic Phase/Position Detection

1.1.4. 24-bit Parallel Output



Supports 24-bit RGB/YC

4:4:4 and 12-bit

RGB/YC

4:4:4 Double Data Rate (DDR) modes

Supports 24-bit YC

4:2:2 and 12-bit YC

4:2:2

DDR modes

Supports 8/10/12-bit YC MUX 4:2:2 modes

Supports embedded sync for YC

4:2:2 and YC

MUX 4:2:2 modes

Supports embedded raw VBI data (CC, WSS)

1.1. Features

1.1.1. Analog (Video) Front-end



Four 10-bit Analog-to-Digital Converters (ADC)

sampling up to 170 MHz

Flexible input multiplexers to support four

composite and two component video inputs

Support cable plug-in detection and active video

signal detection

1.2. Applications

The SiI8788 device is targeted at the home theatre and

profession/commercial markets, specifically in A/V

Receiver and Video Switcher / Processor applications

1.3. Packaging



88-pin QFN with exposed pad (ePad)

10 mm × 10 mm × 0.9 mm

1.1.2. Multi-format Video Decoder



Automatic format detection

Supports NTSC, PAL, and SECAM standards of

composite input with adaptive comb filter

Supports 240p/288p, 480i/p, 576i/p, 720p,

1080i/p component video

Supports Macrovision Type I, II, III copy protection

detection

Supports multistandard VBI decoding: WSS, VPS,

CC, CGMS, and V-CHIP

1.4. Temperature Range



C

to +70

C

A/V Receiver

CVBS Pass Through

Analog

Video

Inputs

SiI8788

Parallel Video Output

HDMI

Video

Processor

HDMI

MHL

Port

Processor

Figure 1.1. Typical Application of the SiI8788 Device

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1123-A