SiT2002B
High Frequency, Single Chip, SOT23 Oscillator
Features
Applications
Any frequency between 115 MHz to 137 MHz accurate
to 6 decimal places of accuracy
Operating temperature from -40°C to 85°C.
Refer to
SiT2019
for -40°C to 125°C and
SiT2021
for -55°C to 125°C options
Excellent total frequency stability as low as ±20 PPM
Low power consumption of 4.9 mA typical at 1.8V
LVCMOS/LVTTL compatible output
5-pin SOT23-5: 2.9 mm x 2.8 mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to
SiT2024
and
SiT2025
GEPON, network switches, routers, servers,
embedded systems, industrial and medical devices
Ethernet, PCI-E, DDR, etc.
Electrical Specifications
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
115
-20
-25
-50
Operating Temperature Range
(Ambient)
T_use
-20
-40
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
Standby Current
I_od
I_std
–
–
–
–
–
Typ.
–
–
–
–
–
–
1.8
2.5
2.8
3.0
3.3
–
6.2
5.5
4.9
–
–
2.6
1.4
0.6
Max.
137
+20
+25
+50
+70
+85
1.98
2.75
3.08
3.3
3.63
3.63
7.5
6.4
5.6
4.3
4.1
4.3
2.5
1.3
Unit
MHz
PPM
PPM
PPM
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
No load condition, f = 125 MHz, Vdd = 2.8V, 3.0V, 3.3V or
2.25 to 3.63V
No load condition, f = 125 MHz, Vdd = 2.5V
No load condition, f = 125 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = Low, Output in high Z state
Vdd = 1.8V, OE = Low, Output in high Z state
Vdd = 2.8V to 3.3V,
ST
= Low, Output is weakly pulled down
Vdd = 2.5V,
ST
= Low, Output is weakly pulled down
Vdd = 1.8V,
ST
= Low, Output is weakly pulled down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Extended Commercial
Industrial
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Condition
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Supply Voltage and Current Consumption
Supply Voltage
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
–
–
1.0
1.3
1.0
–
–
55
2.0
2.5
2.0
–
%
ns
ns
ns
Vdd
Output Low Voltage
VOL
10%
Vdd
Rev. 1.02
April 19, 2018
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SiT2002B
High Frequency, Single Chip, SOT23 Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
Symbol
VIH
VIL
Z_in
Min.
70%
–
50
2
Startup Time
Enable/Disable Time
Resume Time
RMS Period Jitter
T_start
T_oe
T_resume
T_jitt
–
–
–
–
–
Peak-to-peak Period Jitter
T_pk
–
–
RMS Phase Jitter (random)
T_phj
–
–
Typ.
–
–
87
–
–
–
–
1.9
1.6
12
14
0.5
1.3
Max.
–
30%
150
–
5
130
5
Jitter
3
4
20
30
0.9
2
ps
ps
ps
ps
ps
ps
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 125 MHz, Vdd = 1.8V
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 125 MHz, Vdd = 1.8V
Integration bandwidth = 900 kHz to 7.5 MHz
Integration bandwidth = 12 kHz to 20 MHz
Unit
Vdd
Vdd
k
M
ms
ns
ms
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Condition
Input Characteristics
Startup and Resume Timing
Measured from the time Vdd reaches its rated minimum value
f = 115 MHz.
For other frequencies, T_oe = 100 ns + 3 * clock periods
Measured from the time
ST
pin crosses 50% threshold
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output Enable
Functionality
Electrical ground
No connect
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open : specified frequency output
3
OE /
ST
/NC
Standby
L: output is low (weak pull down). Device goes to sleep mode.
Supply current reduces to I_std.
Any voltage between 0 and Vdd or Open :
Specified frequency output. Pin 3 has no function.
Power supply voltage
Oscillator output
[2]
[1]
[1]
[1]
Top View
OE /
/ NC
NC
GND
No Connect
4
5
VDD
OUT
Power
Output
VDD
OUT
Figure 1. Pin Assignments
Notes:
1. In OE or
ST
mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC
option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev. 1.02
Page 2 of 16
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SiT2002B
High Frequency, Single Chip, SOT23 Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free
soldering guidelines)
Junction Temperature
[3]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[4]
Package
SOT23-5
JA, 4 Layer Board
(°C/W)
421
JC, Bottom
(°C/W)
175
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature (ambient)
70°C
85°C
Maximum Operating Junction Temperature
80°C
95°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.02
Page 3 of 16
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SiT2002B
High Frequency, Single Chip, SOT23 Oscillator
Test Circuit and Waveform
[6]
Test
Point
Vout
Vdd
tr
80% Vdd
Power
Supply
tf
5
15 pF
(including probe
and fixture
capacitance)
4
0.1µF
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
1
2
3
Vdd
1k
Ω
OE/ST Function
Figure 2. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Output Waveform
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[7]
ST Voltage
T_resume
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
Vdd
50% Vdd
T_oe
OE Voltage
Figure 5. Standby Resume Timing (ST Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Note:
7. SiT2002 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 7. OE Disable Timing (OE Mode Only)
Rev. 1.02
Page 4 of 16
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SiT2002B
High Frequency, Single Chip, SOT23 Oscillator
Performance Plots
[8]
1.8
7.5
20
7.0
6.5
6.0
5.5
5.0
4.5
4.0
115
117
119
121
123
125
127
129
131
133
135
137
15
2.5
2.8
3.0
3.3
DUT1
DUT6
DUT2
DUT7
DUT3
DUT8
DUT4
DUT9
DUT5
DUT10
Frequency (ppm)
10
5
0
-5
-10
-15
-20
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Idd (mA)
Figure 8. Idd vs Frequency
Figure 9. Frequency vs Temperature, 1.8V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
55
54
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
RMS period jitter (ps)
53
Duty cycle (%)
52
51
50
49
48
47
46
45
115
117
119
121
123
125
127
129
131
133
135
137
Figure 10. RMS Period Jitter vs Frequency
Figure 11. Duty Cycle vs Frequency
1.8 V
2.5
2.5 V
2.8 V
3.0 V
3.3 V
2.5
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
Rise time (ns)
2.0
1.5
Fall time (ns)
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Figure 12. 20%-80% Rise Time vs Temperature
Figure 13. 20%-80% Fall Time vs Temperature
Rev. 1.02
Page 5 of 16
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