首页 > 器件类别 > 无源元件 > 振荡器

SIT3372AI-1E3-25EH122.123456Y

LVPECL Output Clock Oscillator, 122.123456MHz Nom, QFN-6

器件类别:无源元件    振荡器   

厂商名称:SiTime

器件标准:

下载文档
器件参数
参数名称
属性值
是否Rohs认证
符合
Objectid
7324340708
包装说明
DILCC6,.2
Reach Compliance Code
unknown
Country Of Origin
Malaysia, Taiwan, Thailand
YTEOL
7.77
其他特性
ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; MIL-STD-883F
最大控制电压
2.25 V
最小控制电压
0.25 V
最长下降时间
0.29 ns
频率调整-机械
NO
频率偏移/牵引率
200 ppm
频率稳定性
50%
JESD-609代码
e4
线性度
1%
安装特点
SURFACE MOUNT
端子数量
6
标称工作频率
122.123456 MHz
最高工作温度
85 °C
最低工作温度
-40 °C
振荡器类型
LVPECL
输出负载
50 OHM
封装等效代码
DILCC6,.2
物理尺寸
7.0mm x 5.0mm x 0.9 mm
最长上升时间
0.29 ns
最大压摆率
92 mA
最大供电电压
2.75 V
最小供电电压
2.25 V
标称供电电压
2.5 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
文档预览
SiT3372
1 MHz to 220 MHz Ultra-low Jitter Differential VCXO
Description
The
SiT3372
is a 1 MHz to 220 MHz differential MEMS
VCXO engineered for low-jitter applications. Utilizing
SiTime’s unique DualMEMS
®
temperature sensing and
TurboCompensation
®
technology, the SiT3372 delivers
exceptional dynamic performance by providing
resistance to airflow, thermal gradients, shock and
vibration. This device also integrates multiple on-chip
regulators to filter power supply noise, eliminating the
need for a dedicated external LDO.
The SiT3372 can be factory programmed for any
combination of frequency, stability, voltage, output
signaling, and pull range. Programmability enables
designers to optimize clock configurations while
eliminating long lead times and customization costs
associated with quartz devices where each frequency is
custom built.
The wide frequency range and programmability makes
this device ideal for telecom, networking, and industrial
applications that require a variety of pullable frequencies
and operate in noisy environments.
Refer to
Manufacturing Notes
for proper reflow profile,
tape and reel dimension, and other manufacturing
related information.
Features
Any frequency between 1 MHz and 220 MHz accurate
to 6 decimal places
(For frequencies 220.000001 MHz to 725 MHz, refer
to
SiT3373)
Widest pull range options: ±25, ±50, ±80, ±100, ±150,
±200, ±400, ±800, ±1600, ±3200 ppm
0.225 ps RMS phase jitter (typ) over 12 kHz to 20 MHz
bandwidth
Frequency stability as low as
±15
ppm
Wide temperature range support from -40°C to 105°C
Industry-standard packages: 7.0 x 5.0 mm,
5.0 x 3.2 mm, 3.2 x 2.5 mm packages
Applications
Cable Modem Termination System (CMTS), Video,
Broadcasting System, Audio, Industrial Sensors,
Remote Radio Head (RRH)
SATA, SAS, 10/40/100/400 Gbps Ethernet, Fibre Channel,
PCI-Express
Block Diagram
3.2 x 2.5 mm Package Pinout
VIN
NC
GND
1
6
VDD
OUT-
OUT+
2
5
3
4
Figure 1. SiT3372 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 6
for Pin Descriptions)
Rev 1.07
20 July 2021
www.sitime.com
SiT3372
1 MHz to 220 MHz Ultra-low Jitter Differential VCXO
Ordering Information
SiT3372AC -1B2-33NH122.123456T
Part Family
“SiT3372”
Packaging
“T”, “Y”, “D” or “E”
Refer to table below for packing method
[1]
Leave Blank for Bulk
Revision Letter
“A” is the revision of Silicon
Frequency
1.000000 MHz to 220.000000 MHz
Temperature Range
“C”: Extended Commercial, -20 to 70°C
“ I ” : Industrial, -40 to 85°C
“B”: -40 to 95°C
“E”: Extended Industrial, -40 to 105°C
Pull Range Options
“M”: ±25 ppm
“B”: ±50 ppm
“C”: ±80 ppm
“E”: ±100 ppm
“G”: ±150 ppm
“H”: ±200 ppm
“X”: ±400 ppm
“Y”: ±800 ppm
“Z”: ±1600 ppm
“U”: ±3200 ppm
[2]
Signalling Type
“1”: LVPECL
“2”: LVDS
“4”: HCSL
Package Size
“B”: 3.2 x 2.5 mm
“C”: 5.0 x 3.2 mm with center pad
“E”: 7.0 x 5.0 mm with center pad
Feature Pin
[3]
“N”: No Connect
“E”: Output Enable
Frequency Stability
“H”:
“2”:
“9”:
“3”:
±15 ppm
±25 ppm
±35 ppm
±50 ppm
Voltage Supply
“25”: 2.5 V ±10%
“28”: 2.8 V ±10%
“30”: 3.0 V ±10%
“33”: 3.3 V ±10%
Notes:
1. Bulk is available for sampling only.
2.
Contact SiTime
for custom pull range options.
3. “E”: Output Enable function is only available in 7.0 x 5.0 mm and 5.0 x 3.2 mm packages.
Table 1. Ordering Codes for Supported Tape & Reel Packing Method
Device Size
(mm x mm)
7.0 x 5.0
5.0 x 3.2
3.2 x 2.5
8 mm T&R
(3ku)
D
8 mm T&R
(1ku)
E
12 mm T&R
(3ku)
T
T
12 mm T&R
(1ku)
Y
Y
16 mm T&R
(3ku)
T
16 mm T&R
(1ku)
Y
Rev 1.07
Page 2 of 17
www.sitime.com
SiT3372
1 MHz to 220 MHz Ultra-low Jitter Differential VCXO
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics.............................................................................................................................................................. 4
Waveform Diagrams .................................................................................................................................................................. 10
Timing Diagrams ........................................................................................................................................................................ 11
Termination Diagrams................................................................................................................................................................ 12
LVPECL .............................................................................................................................................................................. 12
LVDS .................................................................................................................................................................................. 13
HCSL .................................................................................................................................................................................. 13
Dimensions and Patterns ― 3.2 x 2.5 mm................................................................................................................................. 14
Dimensions and Patterns ― 5.0 x 3.2 mm................................................................................................................................. 14
Dimensions and Patterns ― 7.0 x 5.0 mm................................................................................................................................. 15
Additional Information ................................................................................................................................................................ 16
Revision History ......................................................................................................................................................................... 17
Rev 1.07
Page 3 of 17
www.sitime.com
SiT3372
1 MHz to 220 MHz Ultra-low Jitter Differential VCXO
Electrical Characteristics
Table 2. Electrical Characteristics – Common to LVPECL, LVDS and HCSL
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with standard
output termination shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-15
-25
-35
-50
Operating Temperature Range
T_use
-20
-40
-40
-40
Supply Voltage
Vdd
2.97
2.7
2.52
2.25
Pull Range
PR
Typ.
3.3
3.0
2.8
2.5
Max.
220
+15
+25
+35
+50
+70
+85
+95
+105
3.63
3.3
3.08
2.75
Unit
MHz
ppm
ppm
ppm
ppm
°C
°C
°C
°C
V
V
V
V
ppm
See the APR (Absolute Pull Range)
Table 11.
Contact SiTime
for custom pull range options
Voltage at which maximum frequency deviation is guaranteed
Voltage at which minimum frequency deviation is guaranteed
Contact SiTime
for other input bandwidth options
Extended Industrial
Extended Commercial
Industrial
Condition
Accurate to 6 decimal places
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, load variations, and first year aging at 25
°C,
with VIN voltage at Vdd/2.
±15
ppm is only guaranteed for pull range up to
±100
ppm.
Frequency Range
Frequency Stability
Temperature Range
Supply Voltage
Voltage Control Characteristics
±25, ±50, ±80, ±100, ±150,
±200, ±400, ±800, ±1600,
±3200
90%
10
10
10%
1.0
Input Characteristics
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Duty Cycle
Startup Time
OE Enable/Disable Time
VIH
VIL
Z_in
DC
T_start
T_oe
70%
45
100
30%
-
55
3.0
3.8
Vdd
Vdd
%
ms
µs
Measured from the time Vdd reaches its rated minimum value
f = 156.25 MHz. Measured from the time OE pin reaches
rated VIH and VIL to the time clock pins reach 90% of swing
and high-Z. See
Figure 9
and
Figure 10
Pin 2, OE
Pin 2, OE
Pin 2, OE logic high or logic low
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Pull Range Linearity
Frequency Change Polarity
VC_U
VC_L
VC_z
V_c
Lin
Vdd
Vdd
kHz
%
Positive Slope
Output Characteristics
Startup and OE Timing
Rev 1.07
Page 4 of 17
www.sitime.com
SiT3372
1 MHz to 220 MHz Ultra-low Jitter Differential VCXO
Table 3. Electrical Characteristics – LVPECL Specific
Parameter
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
RMS Period Jitter
[4]
RMS Phase Jitter (random)
Symbol
Idd
I_OE
I_leak
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_jitt
T_phj
Min.
Vdd-1.15
Vdd-2.0
1.2
Typ.
78
53
0.15
1.6
225
1.0
0.225
Max.
92
61
33
Vdd-0.7
Vdd-1.5
2.0
290
1.6
0.270
Unit
mA
mA
A
mA
V
V
V
ps
ps
ps
Condition
Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V
OE = Low
OE = Low
Maximum average current drawn from OUT+ or OUT-
See
Figure 5
See
Figure 5
See
Figure 6
20% to 80%, see
Figure 6
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -20 to 70°C and -40 to 85°C
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -40 to 95°C and -40 to 105°C
f = 156.25 MHz, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, includes spurs, all Vdd
levels
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -20 to 70°C and -40 to 85°C
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -40 to 95°C and -40 to 105°C
f = 156.25 MHz, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, includes spurs, all
Vdd levels
Current Consumption
Output Characteristics
Jitter – 7.0 x 5.0 mm package
0.225
0.300
ps
0.1
ps
Jitter – 5.0 x 3.2 mm and 3.2 x 2.5 mm package
RMS Period
Jitter
[4]
T_jitt
T_phj
1.0
0.225
1.6
0.275
ps
ps
RMS Phase Jitter (random)
0.225
0.340
ps
0.1
ps
Notes:
4. Measured according to JESD65B.
Rev 1.07
Page 5 of 17
www.sitime.com
查看更多>
ATmega8实现的电视字幕叠加器
随着数字电视和VOD的推广和流行,这种基于硬件的字幕叠加器恐怕很快就要过时了,但是在某些场合或...
某某人 单片机
6个盘片有几个磁头?怎样计算
遇到一个问题, 某硬盘盘片由6片组成,则 他的磁头数为多少? 有人说是11个,不知道对不对. 告诉我...
teikou 嵌入式系统
ubuntu下gedit不能用解决方法
ubuntu下gedit不能用解决方法 分类: LINUX su root 后出现不能用...
regove Linux与安卓
各个商家的ARM架构的优缺点
瑞萨、飞思卡尔、Microchip、NEC、Atmel等等这些MCU大鳄都拥有自己的ARM架构。如今...
墨秋晓 ARM技术
[ESP32-Audio-Kit音频开发板测评]五、读一下ID
这个跑起来我觉得比上个还简单,直接找到读ID的例程 然后点向右键头的编译下载,并按住BOOT键,...
ddllxxrr RF/无线
利用I2C总线读写AT24C512的FPGA原创代码
根据上面一篇研究AT24C512的DATASHEET 心得,设计如下利用FPGA读写 AT24C...
eeleader FPGA/CPLD
热门器件
热门资源推荐
器件捷径:
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ
需要登录后才可以下载。
登录取消