Features .......................................................................................................................................................................................1
Ordering Information .....................................................................................................................................................................2
Dimensions and Patterns ― 3.2 x 2.5 mm .................................................................................................................................14
Dimensions and Patterns ― 5.0 x 3.2 mm .................................................................................................................................14
Dimensions and Patterns ― 7.0 x 5.0 mm .................................................................................................................................15
Additional Information .................................................................................................................................................................16
Revision History ..........................................................................................................................................................................17
Rev 1.07
Page 3 of 17
www.sitime.com
SiT3373
220 MHz to 725 MHz Ultra-low Jitter Differential VCXO
Electrical Characteristics
Table 2. Electrical Characteristics – Common to LVPECL, LVDS and HCSL
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with standard
output termination shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
220.000001
-15
-25
-35
-50
Operating Temperature Range
T_use
-20
-40
-40
-40
Supply Voltage
Vdd
2.97
2.70
2.52
2.25
Pull Range
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Pull Range Linearity
Frequency Change Polarity
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Duty Cycle
Start-up Time
OE Enable/Disable Time
PR
VC_U
VC_L
VC_z
V_c
Lin
–
VIH
VIL
Z_in
DC
T_start
T_oe
70%
–
–
45
–
–
Typ.
–
–
–
–
–
–
–
–
–
3.30
3.00
2.80
2.50
Max.
725
+15
+25
+35
+50
+70
+85
+95
+105
Supply Voltage
3.63
3.30
3.08
2.75
V
V
V
V
ppm
Vdd
Vdd
MΩ
kHz
%
–
–
30%
-
55
3.0
3.8
Vdd
Vdd
kΩ
%
ms
µs
Measured from the time Vdd reaches its rated minimum value.
f = 322.265625 MHz. Measured from the time OE pin reaches
rated VIH and VIL to the time clock pins reach 90% of swing
and high-Z. See
Figure 9
and
Figure 10
Pin 2, OE
Pin 2, OE
Pin 2, OE logic high or logic low
Contact SiTime
for other input bandwidth options
See the APR (Absolute Pull Range)
Table 11.
Contact SiTime
for custom pull range options
Voltage at which maximum frequency deviation is guaranteed
Voltage at which minimum frequency deviation is guaranteed
Unit
MHz
ppm
ppm
ppm
ppm
°C
°C
°C
°C
Extended Industrial
Extended Commercial
Industrial
Condition
Accurate to 6 decimal places
Inclusive of initial tolerance, operating temperature, rated
power supply voltage, load variations, and first year aging
at 25°C, with VIN voltage at Vdd/2.
±15
ppm is only guaranteed for pull range up to
±100
ppm.
Frequency Range
Frequency Stability
Temperature Range
Voltage Control Characteristics
±25, ±50, ±80, ±100, ±150, ±200,
±400, ±800, ±1600, ±3200
90%
–
–
–
–
–
–
10
10
–
Positive Slope
–
–
100
–
–
–
–
10%
–
–
1.0
Input Characteristics
Output Characteristics
Startup and OE Timing
Rev 1.07
Page 4 of 17
www.sitime.com
SiT3373
220 MHz to 725 MHz Ultra-low Jitter Differential VCXO
Table 3. Electrical Characteristics – LVPECL Specific
Parameter
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
RMS Period Jitter
[4]
RMS Phase Jitter (random)
Symbol
Idd
I_OE
I_leak
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_jitt
T_phj
–
0.220
0.270
ps
Min.
–
–
–
–
Vdd-1.15
Vdd-1.9
1.2
–
–
Typ.
–
–
0.15
–
–
–
1.6
225
1.0
Max.
97
63
–
32
Vdd-0.7
Vdd-1.5
2.0
290
1.6
Unit
mA
mA
A
mA
V
V
V
ps
ps
Condition
Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V
OE = Low
OE = Low
Maximum average current drawn from OUT+ or OUT-
See
Figure 5
See
Figure 5
See
Figure 6
20% to 80%, see
Figure 6
f = 322.265625 MHz, Vdd = 3.3 V or 2.5 V
f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs, pull range =
±100
ppm.
Temperature ranges -20 to 70°C and -40 to 85°C
f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs, pull range =
±100
ppm.
Temperature ranges -40 to 95°C and -40 to 105°C
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10 GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz,
all Vdd levels
f = 322.265625 MHz, Vdd = 3.3 V or 2.5 V
f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs, pull range =
±100
ppm.
Temperature ranges -20 to 70°C and -40 to 85°C
f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs, pull range =
±100
ppm.
Temperature ranges -40 to 95°C and -40 to 105°C
f = 322.265625 MHz, IEEE802.3-2005 10 GbE jitter mask
integration bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
例程： /* Configure one bit for preemption priority */ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); /* Enable the WAKEUP_BUTTON_EXTI_IRQn Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_...[详细]
Note: Initializing or Re-Configuring the USART Module The required USART initialization/re-configuration process is: 1) Set SWRST (BIS.B #SWRST,&UxCTL) 2) Initialize all USART registers with SWRST = ...[详细]
FPGA/CPLD
