Ordering Information .................................................................................................................................................................... 2
7.1. User Programming Interface ..................................................................................................................................... 19
7.2. Start-up output frequency and signaling types .......................................................................................................... 19
8.1. Any-frequency function ............................................................................................................................................. 20
9 I C/SPI Control Registers...................................................................................................................................................... 29
9.1. Register Address: 0x00. DCO Frequency Control Least Significant Word (LSW) .................................................... 29
9.2. Register Address: 0x01. OE Control, DCO Frequency Control Most Significant Word (MSW) ................................. 30
9.3. Register Address: 0x02. DCO PULL RANGE CONTROL ........................................................................................ 31
9.4. Register Address: 0x03. Flac-N PLL Integer Value and Flac-N PLL Fraction MSW ................................................. 32
9.6. Register Address: 0x05. PostDiv, Driver Control ...................................................................................................... 33
9.7. Register Address: 0x06. mDriver, Driver Control ...................................................................................................... 34
2
10 I C Operation ........................................................................................................................................................................ 35
2
10.1. I C protocol ............................................................................................................................................................... 35
2
10.2. I C Timing Specification ............................................................................................................................................ 37
2
10.3. I C Device Address Modes ....................................................................................................................................... 38
Dimensions and Patterns ........................................................................................................................................................... 45
Additional Information ................................................................................................................................................................ 46
Revision History ......................................................................................................................................................................... 47
Rev 0.991
Page 3 of 47
www.sitime.com
SiT3521
1 to 340 MHz Elite™ I
2
C/SPI Programmable Oscillator
1 Electrical Characteristics
PRELIMINARY
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with
standard output terminations shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics – Common to LVPECL, LVDS and HCSL
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-10
-20
-25
-50
First Year Aging
Operating Temperature Range
F_1y
T_use
–
-20
-40
-40
Supply Voltage
Vdd
2.97
2.7
2.52
2.25
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Duty Cycle
Start-up Time
Output Enable/Disable Time –
Hardware control via OE pin
Output Enable/Disable Time –
Software control via I
2
C/SPI
VIH
VIL
Z_in
DC
T_start
T_oe_hw
70%
–
–
45
–
–
Typ.
–
–
–
–
–
±1
–
–
–
3.3
3.0
2.8
2.5
–
–
100
–
–
–
Max.
340
+10
+20
+25
+50
–
+70
+85
+105
Supply Voltage
3.63
3.3
3.08
2.75
–
30%
–
55
3.0
3.8
V
V
V
V
Vdd
Vdd
kΩ
%
ms
µs
Measured from the time Vdd reaches its rated minimum value
Measured from the time OE pin reaches rated VIH and VIL to
the time clock pins reach 90% of swing and high-Z.
See
Figure 9
and
Figure 10
Measured from the time the last byte of command is
transmitted via I
2
C/SPI (reg1) to the time clock pins reach 90%
of swing and high-Z. See
Figure 30
and
Figure 31
OE pin
OE pin
OE pin, logic high or logic low
Unit
MHz
ppm
ppm
ppm
ppm
ppm
°C
°C
°C
1 -year aging at 25°C
Extended Commercial
Industrial
Extended Industrial. Available only for I C operation, not SPI.
2
st
Condition
Factory or user programmable, accurate to 6 decimal places
Inclusive of initial tolerance, operating temperature, rated
power supply voltage and load variations.
Frequency Range
Frequency Stability
Temperature Range
Input Characteristics – OE Pin
Output Characteristics
Startup and Output Enable/Disable Timing
T_oe_sw
–
–
6.5
µs
Rev 0.991
Page 4 of 47
www.sitime.com
SiT3521
1 to 340 MHz Elite™ I
2
C/SPI Programmable Oscillator
Table 2. Electrical Characteristics – LVPECL Specific
Parameter
Symbol
Min.
Typ.
Max.
Unit
PRELIMINARY
Condition
Current Consumption
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Maximum Output Current
Idd
I_OE
I_leak
I_driver
–
–
–
–
–
–
0.15
–
89
58
–
32
mA
mA
A
mA
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
Maximum average current drawn from OUT+ or OUT-
Output Characteristics
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
VOH
VOL
V_Swing
Tr, Tf
Vdd - 1.1V
Vdd - 1.9V
1.2
–
–
–
1.6
225
Vdd - 0.7V
Vdd - 1.5V
2.0
290
Jitter
RMS Phase Jitter (random) –
DCO Mode Only
T_phj
–
–
RMS Phase Jitter (random) –
Any-frequency Mode Only
T_phj
–
–
RMS Period Jitter
[3]
Note:
3. Measured according to JESD65B.
T_jitt
–
0.225
0.1
0.225
0.11
1
0.340
0.14
0.340
0.15
1.6
ps
ps
ps
ps
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
V
V
V
ps
See
Figure 5
See
Figure 5
See
Figure 6
20% to 80%, see
Figure 6
Table 3. Electrical Characteristics – LVDS Specific
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Current Consumption
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Idd
I_OE
I_leak
–
–
–
–
–
0.15
80
61
–
mA
mA
A
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
Output Characteristics
Differential Output Voltage
Delta VOD
Offset Voltage
Delta VOS
Rise/Fall Time
VOD
ΔVOD
VOS
ΔVOS
Tr, Tf
250
–
1.125
–
–
–
–
–
–
400
455
50
1.375
50
470
Jitter
RMS Phase Jitter (random) –
DCO Mode Only
T_phj
–
–
RMS Phase Jitter (random) –
Any-frequency Mode Only
T_phj
–
–
RMS Period Jitter
[4]
Note:
4. Measured according to JESD65B.
T_jitt
–
0.21
0.1
0.21
0.1
1
0.275
0.12
0.367
0.12
1.6
ps
ps
ps
ps
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
mV
mV
V
mV
ps
f = 156.25MHz See
Figure 7
See
Figure 7
See
Figure 7
See
Figure 7
Measured with 2 pF capacitive loading to GND, 20% to 80%,
华为
David De Cremer与田涛
眼光长远、能创造共同价值的高效组织将成为未来的典范，但目前这类组织仍非常少见。当前的问题在于，绩效制度过于关注结果，而忽略了工作中的人性因素。然而，人性因素也会影响制度本身的有效性。的确，人们仍认为基于组织理性行为量身制定的制度可以提高绩效，因此在设计组织制度时，对感情、非理性和心理因素缺乏重视。对人类决策缺陷的研究发现，一个理性的人...[详细]
测试/测量
