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SIT3542ACA1C2281SG622.080000

LVPECL Output Clock Oscillator, 622.08MHz Nom, QFN, 10 PIN

器件类别:无源元件    振荡器   

厂商名称:SiTime

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
Objectid
145148593987
包装说明
LCC10,.12X.2,50/40
Reach Compliance Code
unknown
Country Of Origin
Malaysia, Taiwan, Thailand
YTEOL
6.79
其他特性
ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT
最长下降时间
0.29 ns
频率调整-机械
NO
频率稳定性
25%
JESD-609代码
e4
安装特点
SURFACE MOUNT
端子数量
10
标称工作频率
622.08 MHz
最高工作温度
70 °C
最低工作温度
-20 °C
振荡器类型
LVPECL
输出负载
50 OHM
封装等效代码
LCC10,.12X.2,50/40
物理尺寸
5.0mm x 3.2mm x 0.9mm
最长上升时间
0.29 ns
最大供电电压
3.08 V
最小供电电压
2.52 V
标称供电电压
2.8 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
文档预览
SiT3542
340 to 725 MHz Endura™ Series I
2
C/SPI Programmable Oscillator
Features
Description
The
SiT3542
is a ruggedized, ultra-low jitter, user
programmable oscillator with a maximum acceleration
sensitivity of 0.1 ppb/g. SiT3542, designed for high reliability
applications, offers the system designer great flexibility and
functionality in the most demanding environments.
The device supports two in-system programming options
after powering up at a default, factory programmed startup
frequency:
0.1 ppb/g acceleration sensitivity for harsh environments
Programmable frequencies (factory or via I
2
C/SPI)
from 340.000001 MHz to 725 MHz
Digital frequency pulling (DCO) via I
2
C/SPI
Output frequency pulling with perfect pull linearity
13 programmable pull range options to
±3200
ppm
Frequency pull resolution as low as 5 ppt (0.005 ppb)
0.21 ps typical integrated phase jitter (12 kHz to 20 MHz)
Integrated LDO for on-chip power supply noise filtering
0.02 ps/mV PSNR
-40°C to 105°C operating temperature
LVPECL, LVDS, or HCSL outputs
Programmable LVPECL, LVDS Swing
LVDS Common Mode Voltage Control
RoHS and REACH compliant, Pb-free, Halogen-free
and Antimony-free
Any-frequency mode where the clock output can be re-
programmed to any frequency between 340 MHz and
725 MHz in 1 Hz steps
Digitally controlled oscillator (DCO) mode where the
clock output can be steered or pulled by up to
±3200
ppm with 5 to 94 ppt (parts per trillion) resolution.
A user specifies the device’s default start-up frequency in
the ordering code. User programming of the device is
achieved via I
2
C or SPI. Up to 16 I
2
C addresses can be
specified by the user either as a factory programmable
option or via hardware pins, enabling the device to share
the I
2
C with other I
2
C devices.
The SiT3542 utilizes SiTime’s unique DualMEMS™
temperature sensing and TurboCompensation™ technology
to deliver exceptional dynamic performance
Applications
Land Mobile Communications
Avionics
Airframe / Engine Management Control
Satellite Base Stations
Resistant to airflow and thermal shock
Resistant to shock and vibration
Superior power supply noise rejection
Block Diagram
Package Pinout
(10-Lead QFN, 5.0 x 3.2 mm)
O
IS
M
A/ K
SD C L
S
10
9
OE / NC
OE / NC
GND
1
8
VDD
OUT-
OUT+
2
7
3
4
5
6
A1 A0
/N /N
C/ C/
M SS
O
SI
Figure 1. SiT3542 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 14
for Pin Descriptions)
Rev 1.00
July 24, 2020
www.sitime.com
SiT3542
340 to 725 MHz Endura™ Series I
2
C/SPI Programmable Oscillator
Ordering Information
SiT3542 AC A1C133 1 GG622.080000T
Part Family
“SiT3542”
[2]
Revision Letter
“A” is the revision of Silicon
Frequency
Temperature Range
[1]
“I” : Industrial, -40 to 85°C
“C”: Extended Commercial, -20 to 70°C
Special Features
“A” for Low g-Sensitivity, 0.1ppb/g
340. 000001 to 725. 000000 MHz
DCXO Pull Range
“M”
:
“B”
:
“C”
:
“E”
:
“F”
:
“G”
:
“H”
:
“X”
:
“L”
:
“Y”
:
“S”
:
“Z”
:
“U”
:
± 25 ppm
± 50 ppm
± 80 ppm
±100 ppm
±125 ppm
±150 ppm
±200 ppm
±400 ppm
± 600 ppm
±800 ppm
±1200 ppm
±1600 ppm
±3200 ppm
Signaling Type
“1”: LVPECL
“2”: LVDS
“4”: HCSL
Package Size
“C”: 5. 0 x 3. 2 mm
Frequency Stability/Grade
“F”: ±10 ppm
“1”: ±20 ppm
“2”: ±25 ppm
“3”: ±50 ppm
Serial IF mode
“S”
: SPI mode
“0-G”
: I
2
C mode (See below)
I C Factory Programmable Addresses
2
“0-F” : I C Address factory programmed
Sets Bits 3: 0 of Device I
2
C address to
the Hex value of the ordering code .
2
When the I C address is factory
programmed using these codes ,
pin A0, A1 are NC
“G”: I
2
C address controlled by A0, A1 pins
I
2
C Address
1100000
1100010
1101000
1101010 (default)
2
Voltage Supply
“25” : 2. 5 V ±10%
“28” : 2.8 V ±10%
“30” : 3.0 V ±10%
“33” : 3. 3 V ±10%
OE Pin Control
“-”: OE under software Control.
Pin 1 and 2 are both NC.
“1”: Pin 1 OE, Pin 2 NC
“2”: Pin 1 NC, Pin 2 OE
Notes:
1. -40 to 105°C option available only for I
2
C operation.
2. Bulk is available for sampling only.
A1:A0
00
01
10
11
Rev 1.00
Page 2 of 49
www.sitime.com
SiT3542
340 to 725 MHz Endura™ Series I
2
C/SPI Programmable Oscillator
Table of Contents
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
Ordering Information .................................................................................................................................................................... 2
1 Electrical Characteristics ......................................................................................................................................................... 4
2 Device Configurations and Pin-outs ........................................................................................................................................ 9
3 Waveform Diagrams ............................................................................................................................................................. 11
4 Termination Diagrams ........................................................................................................................................................... 13
4.1. LVPECL .................................................................................................................................................................... 13
4.2. LVDS ........................................................................................................................................................................ 15
4.3. HCSL ........................................................................................................................................................................ 16
5 Test Circuit Diagrams ........................................................................................................................................................... 17
6 Architecture Overview ........................................................................................................................................................... 19
7 Functional Overview ............................................................................................................................................................. 19
7.1. User Programming Interface ..................................................................................................................................... 19
7.2. Start-up output frequency and signaling types .......................................................................................................... 19
7.3. In-system programmable options.............................................................................................................................. 19
8 In-system Programmable Functional Description.................................................................................................................. 20
8.1. Any-frequency function ............................................................................................................................................. 20
8.2. DCO Functional Description ..................................................................................................................................... 25
8.3. Pull Range, Absolute Pull Range .............................................................................................................................. 27
8.4. Software OE Functional Description ......................................................................................................................... 29
9 I
2
C/SPI Control Registers...................................................................................................................................................... 30
9.1. Register Address: 0x00. DCO Frequency Control Least Significant Word (LSW) .................................................... 30
9.2. Register Address: 0x01. OE Control, DCO Frequency Control Most Significant Word (MSW) ................................. 31
9.3. Register Address: 0x02. DCO PULL RANGE CONTROL ........................................................................................ 32
9.4. Register Address: 0x03. Frac-N PLL Integer Value and Frac-N PLL Fraction MSW ................................................ 33
9.5. Register Address: 0x04. Frac-N PLL Fraction LSW.................................................................................................. 33
9.6. Register Address: 0x05. PostDiv, Driver Control ...................................................................................................... 34
9.7. Register Address: 0x06. mDriver, Driver Control ...................................................................................................... 35
10 I
2
C Operation ........................................................................................................................................................................ 36
10.1. I
2
C protocol ............................................................................................................................................................... 36
10.2. I
2
C Timing Specification ............................................................................................................................................ 39
10.3. I
2
C Device Address Modes ....................................................................................................................................... 40
11 SPI Operation ....................................................................................................................................................................... 41
Schematic Examples ................................................................................................................................................................. 44
Dimensions and Patterns ........................................................................................................................................................... 47
Additional Information ................................................................................................................................................................ 48
Revision History ......................................................................................................................................................................... 49
Rev 1.00
Page 3 of 49
www.sitime.com
SiT3542
340 to 725 MHz Endura™ Series I
2
C/SPI Programmable Oscillator
1 Electrical Characteristics
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with
standard output terminations shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics – Common to LVPECL, LVDS and HCSL
Parameter
Output Frequency Range
Symbol
f
Min.
340.000001
340.000001
Typ.
Max.
725.000000
500.000000
Unit
MHz
MHz
Condition
LVDS and LVPECL output driver, factory or user
programmable, accurate to 6 decimal places
HCSL output driver, factory or user programmable, accurate to
6 decimal places
Inclusive of initial tolerance, operating temperature, rated
power supply voltage and load variations
Frequency Range
Frequency Stability
Frequency Stability
F_stab
-20
-20
-25
-50
First Year Aging
F_1y
±1
+20
+20
+25
+50
ppm
ppm
ppm
ppm
ppm
1
st
-year aging at 25°C
Temperature Range
Operating Temperature Range
T_use
-20
-40
-40
+70
+85
+105
°C
°C
°C
Extended Commercial
Industrial
Extended Industrial. Available only for I
2
C operation, not SPI.
Rugged Characteristics
Acceleration (g) sensitivity,
Gamma Vector
Supply Voltage
F_g
0.1
Supply Voltage
Vdd
2.97
2.7
2.52
2.25
3.3
3.0
2.8
2.5
100
3.63
3.3
3.08
2.75
30%
V
V
V
V
ppb/g
Low sensitivity grade; total gamma over 3 axes; 15 Hz to
2 kHz; MIL-PRF-55310, computed per section 4.8.18.3.1
Input Characteristics – OE Pin
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
VIH
VIL
Z_in
70%
Vdd
Vdd
OE pin
OE pin
OE pin, logic high or logic low
Output Characteristics
Duty Cycle
DC
45
55
%
Startup and Output Enable/Disable Timing
Start-up Time
Output Enable/Disable Time –
Hardware control via OE pin
Output Enable/Disable Time –
Software control via I
2
C/SPI
T_start
T_oe_hw
3.0
9.1
ms
µs
Measured from the time Vdd reaches its rated minimum value
Measured from the time OE pin reaches rated VIH and VIL to
the time clock pins reach 90% of swing and high-Z.
See
Figure 9
and
Figure 10
Measured from the time the last byte of command is
transmitted via I
2
C/SPI (reg1) to the time clock pins reach 90%
of swing and high-Z. See
Figure 30
and
Figure 31
T_oe_sw
11.8
µs
Rev 1.00
Page 4 of 49
www.sitime.com
SiT3542
340 to 725 MHz Endura™ Series I
2
C/SPI Programmable Oscillator
Table 2. Electrical Characteristics – LVPECL Specific
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Current Consumption
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Maximum Output Current
Idd
I_OE
I_leak
I_driver
0.10
94
63
30
mA
mA
A
mA
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
Maximum average current drawn from OUT+ or OUT-
Output Characteristics
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
VOH
VOL
V_Swing
Tr, Tf
Vdd - 1.1V
Vdd - 1.9V
1.2
1.6
225
Vdd - 0.7V
Vdd - 1.5V
2.0
290
Jitter
RMS Phase Jitter (random) –
DCO Mode Only
T_phj
RMS Phase Jitter (random) –
Any-frequency Mode Only
T_phj
RMS Period Jitter
[3]
Note:
3. Measured according to JESD65B
T_jitt
0.22
0.075
0.23
0.09
1
0.260
0.085
0.325
0.095
1.6
ps
ps
ps
ps
ps
f = 622.08 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 622.08, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 622.08 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 622.08, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 622.08 MHz, Vdd = 3.3V or 2.5V
V
V
V
ps
See
Figure 5
See
Figure 5
See
Figure 6
20% to 80%, see
Figure 6
Table 3. Electrical Characteristics – LVDS Specific
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Current Consumption
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Idd
I_OE
I_leak
0.15
89
67
mA
mA
A
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
Output Characteristics
Differential Output Voltage
Delta VOD
Offset Voltage
Delta VOS
Rise/Fall Time
VOD
ΔVOD
VOS
ΔVOS
Tr, Tf
250
1.125
340
530
50
1.375
50
460
Jitter
RMS Phase Jitter (random) –
DCO Mode Only
T_phj
RMS Phase Jitter (random) –
Any-frequency Mode Only
T_phj
RMS Period Jitter
[4]
Note:
4. Measured according to JESD65B.
T_jitt
0.21
0.060
0.21
0.070
1
0.255
0.070
0.320
0.80
1.6
ps
ps
ps
ps
ps
f = 622.08 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 622.08 MHz, IEEE802.3-2005 10 GbE jitter mask
integration bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 622.08 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels
f = 622.08 MHz, IEEE802.3-2005 10 GbE jitter mask
integration bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
f = 622.08 MHz, Vdd = 3.3V or 2.5V
mV
mV
V
mV
ps
f = 622.08 MHz. See
Figure 7
See
Figure 7
See
Figure 7
See
Figure 7
Measured with 2 pF capacitive loading to GND, 20% to 80%,
see
Figure 8
Rev 1.00
Page 5 of 49
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00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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