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SIT3821AI-1DF-33EH80.000000T

OSC VCXO 80.0000MHZ LVPECL SMD

器件类别:无源元件   

厂商名称:SiTime

器件标准:

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器件参数
参数名称
属性值
类型
VCXO
频率
80MHz
功能
启用/禁用
输出
LVPECL
电压 - 电源
3.3V
频率稳定度
±10ppm
绝对牵引范围(APR)
±185ppm
工作温度
-40°C ~ 85°C
电流 - 电源(最大值)
69mA
安装类型
表面贴装
封装/外壳
6-SMD,无引线
大小/尺寸
0.276" 长 x 0.197" 宽(7.00mm x 5.00mm)
高度 - 安装(最大值)
0.039"(1.00mm)
电流 - 电源(禁用)(最大值)
35mA
文档预览
SiT3821
1-220 MHz High Performance Differential VCXO
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Any frequency between 1 MHz and 220 MHz accurate to 6 decimal
places
Widest pull range options: ±25, ±50, ±100, ±150, ±200, ±400, ±800,
±1600 ppm
Superior pull range linearity of ≤ 1%, 10 times better than quartz
0.6ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2 mm x 2.5 mm, 5.0 mm x 3.2 mm and
7.0 mm x 5.0 mm
For frequencies higher than 220 MHz, refer to SiT3822 datasheet
Ideal for SONET, Video, Instrumentation, Satellite applications
Telecom, networking, broadband
Electrical Characteristics
Parameter and Conditions
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-10
-25
-50
Operating Temperature Range
Start-up Time
Duty Cycle
Pull Range
Upper Control Voltage
Lower Control Voltage
Linearity
Frequency Change Polarity
Control Voltage Bandwidth (-3dB)
Vin Pin Input Impedance
First Year Aging
10-year Aging
Supply Voltage
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Vdd
Idd
I_OE
I_leak
I-driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
T_use
T_start
DC
PR
VC_U
VC_L
Lin
V_BW
Z_vin
100
-2
-5
2.97
2.25
Vdd-1.1
Vdd-1.9
1.2
-40
-20
45
Typ.
Max.
220
+10
+25
+50
+85
+70
10
55
Unit
MHz
ppm
ppm
ppm
°C
°C
ms
%
ppm
V
V
V
%
+2
+5
3.63
2.75
69
35
1
30
Vdd-0.7
Vdd-1.5
2.0
500
115
1.7
1.7
1.7
0.75
kHz
ppm
ppm
V
V
mA
mA
A
mA
V
V
V
ps
ns
ps
ps
ps
ps
Contact SiTime for 16 kHz or other high bandwidth options
Pin 1
25°C
25°C
Industrial
Extended Commercial
Contact SiTime for tighter duty cycle
See the last page for Absolute Pull Range, APR table
Vdd = 3.3V, Voltage at which maximum deviation is guaranteed
Vdd = 2.5V, Voltage at which maximum deviation is guaranteed
Voltage at which maximum deviation is guaranteed
Condition
LVPECL and LVDS, Common AC Characteristics
Inclusive of initial tolerance, operating temperature, rated
power, supply voltage and load change
±25, ±50, ±100, ±150,
±200, ±400, ±800, ±1600
3.2
2.4
Positive Slope
8
3.3
2.5
61
1.6
300
1.2
1.2
1.2
0.5
0.1
1
LVPECL, DC and AC Characteristics
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
Maximum average current drawn from OUT+ or OUT-
See Figure 1
See Figure 1
See Figure 1
20% to 80%
f = 220 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, Vdd = 3.3V or 2.5V
f = 156.25 MHz, Vdd = 3.3V or 2.5V
f = 212.5 MHz, Vdd = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
RMS Phase Jitter (random)
T_phj
SiTime Corporation
Rev. 1.2
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised October 6, 2014
SiT3821
1-220 MHz High Performance Differential VCXO
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
Parameter and Conditions
Supply Voltage
Current Consumption
OE Disable Current
Output Disable Leakage Current
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Symbol
Vdd
Idd
I_OE
I_leak
VOD
Min.
2.97
2.25
200
1.125
RMS Phase Jitter (random)
T_phj
Typ.
3.3
2.5
47
350
1.2
495
1.2
1.2
1.2
0.6
Max.
3.63
2.75
55
35
1
500
50
1.375
50
600
115
1.7
1.7
1.7
0.85
Unit
V
V
mA
mA
A
mV
mV
V
mV
ps
ns
ps
ps
ps
ps
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
See Figure 4
See Figure 4
See Figure 4
See Figure 4
20% to 80%
f = 220 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, Vdd = 3.3V or 2.5V
f = 156.25 MHz, Vdd = 3.3V or 2.5V
f = 212.5 MHz, Vdd = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
LVDS, DC, and AC Characteristics
VOD
VOS
VOS
Tr, Tf
T_oe
T_jitt
Pin Description
Pin
1
2
3
4
5
6
Map
VIN
NC
OE
GND
OUT+
OUT-
VDD
Input
Input
Input
Power
Output
Output
Power
Control Voltage
No Connect (only for 3225 package)
H or Open: specified frequency output
L: output is high impedance (only for 7050 and 5032 packages)
VDD Power Supply Ground
Oscillator Output
Complementary Oscillator Output
Power Supply Voltage
Functionality
Top View
VIN
NC/OE
GND
1
6
VDD
OUT-
OUT+
2
5
3
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
Max.
150
4
2000
260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050, 6-pin
5032, 6-pin
3225, 6-pin
JA, 4 Layer Board
(°C/W)
142
97
109
JC, Bottom
(°C/W)
27
20
20
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.2
Page 2 of 7
www.sitime.com
SiT3821
1-220 MHz High Performance Differential VCXO
The Smart Timing Choice
The Smart Timing Choice
Termination Diagrams
LVPECL:
VDD
OUT+
D rive D ev ice
OUT-
Z0 = 5 0
50
50
Z 0 = 50
D+
Receiver Device
D-
V T T = V D D – 2.0 V
Figure 1. LVPECL Typical Termination
VDD
OUT+
Drive Device
R1 = 100 to 150
Z0 = 50
100 nF
D+
Receiver Device
100 nF
OUT-
R1
R1
Z0 = 50
50
50
D-
VTT
Figure 2. LVPECL AC Coupled Termination
VDD = 3.3V => R1 = R3 = 133
and
R2 = R4 = 82
VDD = 2.5V => R1 = R3 = 250
and
R2 = R4 = 62.5
VDD
OUT+
Drive Device
OUT-
Z0 = 50
R2
R4
D-
Z0 = 50
VDD
R1
R3
D+
Receiver
Device
Figure 3. LVPECL with Thevenin Typical Termination
Rev. 1.2
Page 3 of 7
www.sitime.com
SiT3821
1-220 MHz High Performance Differential VCXO
The Smart Timing Choice
The Smart Timing Choice
LVDS:
VDD
OUT+
Drive Device
OUT-
Z0 = 50
100
Z0 = 50
D+
Receiver Device
D-
Figure 4. LVDS Single Termination (Load Terminated)
Rev. 1.2
Page 4 of 7
www.sitime.com
SiT3821
1-220 MHz High Performance Differential VCXO
The Smart Timing Choice
The Smart Timing Choice
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[1]
3.2 x 2.5 x 0.75 mm
Recommended Land Pattern (Unit: mm)
[2]
3.2±0.05
#6
#5
#4
#4
2.20
#5
#6
2 .2 5
2.5±0.05
0.7
1.6
YXXXX
0.9
#1
#2
#3
#3
#2
#1
0.6
0.75±0.05
0 .6 5
1 .0 5
5.0 x 3.2 x 0.75 mm
#6
#5
#4
#4
#5
#6
YXXXX
#1
#2
#3
#3
#2
#1
0.75±0.05
7.0 x 5.0 x 0.90 mm
1.20
5.08
7.0±0.10
#6
#5
#4
#4
5.08
#5
#6
5.0±0.10
2.60
1.10
YXXXX
#1
#2
#3
1.40
0.90 ±0.10
1.60
1. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
2. A capacitor of value 0.1
F
between Vdd and GND is recommended.
Rev. 1.2
Page 5 of 7
1.60
www.sitime.com
#3
#2
#1
3.80
1.00
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