SiT3922
Digitally Controlled Differential Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Factory programmable between 220 MHz and 625 MHz accurate to
6 decimal places
Digital controlled pull range
Widest pull range options: ±25, ±50, ±100, ±200, ±400, ±800, ±1600
ppm
Superior pull range linearity of <= 1%, 10 times better than quartz
<0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2 mm x 2.5 mm, 5.0 mm x 3.2 mm and
7.0 mm x 5.0 mm
For frequencies lower than 220 MHz, refer to SiT3921 datasheet
Ideal for SONET, Video, Instrumentation, Satellite applications
Telecom, networking, broadband
Electrical Characteristics
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
220
-10
-25
-50
Operating Temperature Range
Start-up Time
Duty Cycle
Pull Range
Linearity
Frequency Change Polarity
First Year Aging
10-year Aging
Input Low Voltage
Input Middle Voltage
Input High Voltage
Input High or Low Pulse Width
Input Middle Pulse Width
Input to Output Isolation
Input Impedance
Input Capacitance
Zin
Cin
TBD
–
2.97
2.25
–
–
Vdd-1.1
Vdd-1.9
1.2
–
–
RMS Period Jitter
T_jitt
–
–
RMS Phase Jitter (random)
T_phj
–
–
–
3.3
2.5
61
–
–
–
1.6
300
1.2
1.2
1.2
0.6
–
TBD
3.63
2.75
69
30
Vdd-0.7
Vdd-1.5
2.0
500
1.7
1.7
1.7
0.85
VIL
VIM
VIH
T_logic
T_middle
T_use
T_start
DC
PR
Lin
–
-2
-5
–
0.4xVdd
0.8xVdd
500
500
-40
-20
–
45
40
Typ.
–
–
–
–
–
–
–
–
–
Max.
625
+10
+25
+50
+85
+70
10
55
60
Unit
MHz
ppm
ppm
ppm
°C
°C
ms
%
%
ppm
%
–
+2
+5
0.2xVdd
0.6xVdd
–
–
–
ppm
ppm
V
V
V
ns
ns
TBD
k
pF
V
V
mA
mA
V
V
V
ps
ps
ps
ps
ps
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
Maximum average current drawn from OUT+ or OUT-
See Figure 9
See Figure 9
See Figure 9
20% to 80%
f = 266 MHz, Vdd = 3.3V or 2.5V
f = 312.5 MHz, Vdd = 3.3V or 2.5V
f = 622.08 MHz, Vdd = 3.3V or 2.5V
f = 312.5 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdds
Pin 1
Pin 1
25°C
25°C
f = 220 to 314 MHz and f = 528 to 625 MHz
f = 422 to 502 MHz
See the last page for Absolute Pull Range, APR table
Industrial
Extended Commercial
Condition
For frequency coverage see last page
Inclusive of initial tolerance, operating temperature, rated power,
supply voltage and load change
LVPECL and LVDS, Common DC and AC Characteristics
±25, ±50, ±100,
±200, ±400, ±800, ±1600
–
0.1
Positive Slope
–
–
–
–
–
–
–
1
LVPECL, DC and AC Characteristics
Supply Voltage
Current Consumption
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
Vdd
Idd
I-driver
VOH
VOL
V_Swing
Tr, Tf
SiTime Corporation
Rev. 1.1
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised December 2, 2014
SiT3922
Digitally Controlled Differential Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
Parameter and Conditions
Supply Voltage
Current Consumption
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
RMS Period Jitter
Symbol
Vdd
Idd
VOD
Min.
2.97
2.25
–
200
–
1.125
–
–
–
–
–
RMS Phase Jitter (random)
T_phj
–
Typ.
3.3
2.5
47
350
–
1.2
–
495
1.4
1.4
1.2
0.6
Max.
3.63
2.75
55
500
50
1.375
50
600
1.7
1.7
1.7
0.85
Unit
V
V
mA
mV
mV
V
mV
ps
ps
ps
ps
ps
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
See Figure 12
See Figure 12
See Figure 12
See Figure 12
20% to 80%
f = 266 MHz, Vdd = 3.3V or 2.5V
f = 312.5 MHz, Vdd = 3.3V or 2.5V
f = 622.08 MHz, Vdd = 3.3V or 2.5V
f = 312.5 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
LVDS, DC, and AC Characteristics
VOD
VOS
VOS
Tr, Tf
T_jitt
Pin Description
Pin
1
2
3
4
5
6
Map
DP
NC
GND
OUT+
OUT-
VDD
Input
Input
Power
Output
Output
Power
No Connect
VDD power supply ground
Oscillator output
Complementary oscillator output
Power supply voltage
Functionality
Digital programming pin
Top View
DP
NC
GND
1
6
VDD
OUT-
OUT+
2
5
3
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050, 6-pin
5032, 6-pin
3225, 6-pin
JA, 4 Layer Board
(°C/W)
142
97
109
JC, Bottom
(°C/W)
27
20
20
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.1
Page 2 of 11
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SiT3922
Digitally Controlled Differential Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Default Startup Condition
The SiT3922 starts up at its factory programmed frequency and settings. The control register values are initialized all zeros,
effectively setting the frequency to the middle of the control range.
Frequency Control Protocol Description
The device includes two DCXO registers; writing to these registers controls the output frequency. Data for each register is writ-
ten to the device using a data frame.
Data Frame Format
Each frame consists of 40 bits. A frame has 3 parts:
- The header, 16 bit
- Register address, 8 bit
- The data word (represented as 2's complement numbers), 16 bit.
Bits are sent MSB first.
Frames are sent LS word first in mode 2.
The header allows the devices to recognize that the master is initiating communication. The header includes the device
address, which is factory programmable. The valid header is 0xFAIA, where "I" can be a hex digits from 0 to F. If not specified
at the order time, it will be defaulted to zero. In this document in all examples and text, the device address is considered to be
zero (default).
0
15 16
23 24
39
Header
0 x F A 0 A , (1 6 b its )
R e g A d d re s s
0x06 or 0x07
(8 b its )
F re q u e n c y C o n tro l V a lu e
(1 6 b its )
Frequency Control Mode 1
In this resolution mode, only one frame per frequency update is
required, and the output frequency is updated at the end of each
frame. The length of the frequency control data is 16 bits, and is writ-
ten to the device as shown below:
Frequency Control Mode 2
In this mode, two frames per frequency update are required, and fre-
quency is only updated at the end of the second frame. The fre-
quency control value in this mode is 23 bits. This value is written to
the device in two frames as follows:
Figure 1. Frequency Control Mode 1
Figure 2. Frequency Control Mode 2
Resolution and Update Rate for Mode 1
Pull Range (PPM)
Step Resolution (ppb)
1
1.5
3
6
12
25
49
Max Update Rate
(Updates Per Second)
25 K
25 K
25 K
25 K
25 K
25 K
25 K
Resolution and Update Rate for Mode 2
Pull Range (PPM)
Step Resolution (ppb)
1
1
1
1
1
1
1
Max Update Rate
(Updates Per Second)
12.5 K
12.5 K
12.5 K
12.5 K
12.5 K
12.5 K
12.5 K
±25
±50
±100
±200
±400
±800
±1600
±25
±50
±100
±200
±400
±800
±1600
Rev. 1.1
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SiT3922
Digitally Controlled Differential Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
C o n tro l p in
0xFA 0A
0x06
0 x f
1
0xF A D A
0x06
0 x f
2
T
f2 f
O u tp u t
fre q u e n c y
f
0
T
fra m e
T
fd e la y
T
s e ttle
f
0
+ f
1
f
0
+ f
2
Figure 3. Mode 1 Frame Timing
C o n tro l p in
0xFA 0A
0x07
0 x f
1
(L S W )
0xFA D A
0x06
0 x f
1
(M S W )
f
0
+ f
1
O u tp u t
fre q u e n c y
f
0
T
fra m e
T
f2 f
T
fra m e
T
fd e la y
Figure 4. Mode 2 Frame Timing
T
s e ttle
Frame Timing Parameters
Parameter
Frame Length
Frame to Frame Delay
Frequency Settling Time
Frame to Frequency Delay
Symbol
T
frame
T
f2f
T
settle
T
fdelay
Min.
40
2
—
—
Max.
—
—
30
8
Unit
S
S
S
S
Calculating Pull Range PPM offset
The frequency control value must be encoded as a 2's complement number (16-bit in mode 1 and 23-bit in mode 2), represent-
ing the full scale range of the device. For example, for a ±1600ppm device in mode 2, the 23-bit number represents the full
±1600ppm range.
The upper 16 bits of the value are written to address 0x06. If the high-resolution register (address 0x07) is used, the other 7 bits
are written to the lowest seven bits of address 0x07.
Here are the steps to calculate the frequency control value:
1. Find the scale factor (calculated for half of the pull range) from the tables below where PR is the Pull Range:
K (scale)Factor
Mode
K = Scale Factor
1
2
(2^15-1) / (PR*1.00135625)
(2^22-1) / (PR*1.00135625)
2. Enter the desired_PPM in equation below:
Frequency control (decimal value) = round (desired_PPM * K).
3. For any frequency shifts (positive or negative PPM), convert the frequency control value to a 2’s complement binary number.
Rev. 1.1
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SiT3922
Digitally Controlled Differential Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Two examples follow:
Example 1
This example shows how to shift the frequency by +245.6
ppm in a device with ±1600 pull range using Mode 2 (23-bit):
Decimal value: round(245.6 * K) = 642954
23-bit value = 0x09CF8A
LS Word value = 0x000A (to be written to address 0x07)
MS Word value = 0x139F (to be written to address 0x06)
Write LS Word: 0xFA0A 07 000A (Frequency will not
update)
Write MS Word: 0xFA0A 06 139F (Frequency updates
after write)
Example 2
This example shows how to shift the frequency by -831.2
ppm in a device with ±1600 pull range using Mode 2 (23-bit):
Decimal value: round(abs(831.2 * K) = 2175989
23-bit abs binary value: 01000010011001111110101
23-bit 2's comp binary value: 1011110110011000 0001011
LS Word value = 0x 000B
MS Word value = 0x BD98
Write LS Word: 0xFA0A 07 000B (Frequency will not
update)
Write MS Word: 0xFA0A 06 BD98 (Frequency updates
after write)
Physical Interface
The SiTime DCMO uses a serial input interface to adjust the frequency control value. The interface uses a one-wire tri-level
return-to-middle signaling format. Figure 5 below shows the signal waveform of the interface.
T _ b it
“0 ”
0 .8 x V D D
0 .7 x V D D
0 .6 x V D D
0 .4 x V D D
0 .3 x V D D
0 .2 x V D D
T _ b it
“1 ”
V IH
V IM
V IL
T _ lo g ic
T _ lo g ic
T _ m id d le
Figure 5. Serial 1-Wire Tri-Level Signaling
A logical bit “1” is defined by a high-logic followed by mid-logic. A logical bit “0” is defined by a low-logic followed by mid-logic.
The voltage ranges and time durations corresponding to low-logic, high-, and mid-logic are illustrated in Figure 5 and specified
in electrical specification table.
The overall baud rate is computed as below:
baud
_
rate
½
1
T
_
bit
Figure 6 shows a simple circuit to generate tri-level circuit with a general purpose IO (GPIO) with tri-state capability. Most
FPGAs and micro controllers/processors include such GPIOs. If the GPIO does not support tri-state output, two IO s may be
used in combination with external tri-state buffer to generate the tri-level signal; an example of such buffer is the
SN74LVC1G126. The waveform at the output of the tri-state buffer is shown in Figure 7. When the GPIO drives Low or High
voltage, the rise/fall times are typically fast (sub-5ns range). When the output is set to Hi-Z, the output settles at middle voltage
with a RC response. The time constant is determined based on the total capacitance on frequency control pin and the parallel
resistance of the pull-up and pull-down resistors. The time constant in most practical situations will be less than 50ns; this
necessitate choosing longer T_middle to allow the RC waveform to settle within 5% or so.
Rev. 1.1
Page 5 of 11
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