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SIT5156ACCFD128JR-19.123456Y

Clipped Sine Output Oscillator, 19.123456MHz Nom, CQFN, 10 PIN

器件类别：无源元件    振荡器   

厂商名称：SiTime

器件标准：

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器件参数
参数名称
属性值
是否Rohs认证
符合
Objectid
145156914836
包装说明
LCC10,.12X.2,53/47/43
Reach Compliance Code
unknown
老化
1 PPM/FIRST YEAR
频率调整-机械
NO
频率稳定性
2.5%
安装特点
SURFACE MOUNT
端子数量
10
标称工作频率
19.123456 MHz
最高工作温度
70 °C
最低工作温度
-20 °C
振荡器类型
CLIPPED SINE
输出阻抗
10000 Ω
输出电平
0.8 V
封装主体材料
CERAMIC
封装等效代码
LCC10,.12X.2,53/47/43
物理尺寸
5.15mm x 3.35mm x 1.06mm
最大供电电压
3.08 V
最小供电电压
2.52 V
标称供电电压
2.8 V
表面贴装
YES
文档预览
SiT5156
Description
1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Features
The
SiT5156
is a ±0.5 ppm to ±2.5 ppm MEMS Super-
TCXO that is engineered for best dynamic performance. It
is ideal for high reliability telecom, wireless and networking,
industrial, precision GNSS and audio/video applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5156 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5156 offers three device configurations that can be
ordered using
Ordering Codes
for:
Any frequency from 1 MHz to 60 MHz in 1 Hz steps
Factory programmable options for short lead times
Best dynamic stability under airflow, thermal shock
±0.5 ppm stability across temperature
±15 ppb/
°C
typical
frequency slope (ΔF/ΔT)
-40°C to +105°C operating temperature
No activity dips or micro jumps
Resistant to shock, vibration and board bending
On-chip regulators eliminate the need for external LDOs
Digital frequency pulling (DCTCXO) via I
2
C
Digital control of output frequency and pull range
Up to
±3200
ppm pull range
Frequency pull resolution down to 5 ppt
2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
LVCMOS or clipped sinewave output
RoHS and REACH compliant
Pb-free, Halogen-free, Antimony-free
Applications
The SiT5156 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to
Manufacturing Guideline
for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Precision GNSS systems
Microwave backhaul
Network routers and switches
Professional audio and video equipment
Storage and servers
Test and measurement
Block Diagram
5.0 mm x 3.2 mm Package Pinout
SDA / NC
OE / VC / NC
SCL / NC
NC
GND
1
10
9
VDD
NC
NC
CLK
2
3
8
7
4
5
6
A0 / NC
Figure 1. SiT5156 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 13
for Pin Descriptions)
Rev 1.06
May 23, 2020
www.sitime.com
SiT5156
1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime
Part Number Generator.
To validate the part number, use the
SiTime
Part Number Decoder.
Part
Family
Silicon
Revision
Letter
Package Size
"F": 5.0 mm x 3.2 mm
Pin 1 Function
–
TCXO mode only
"E": Output Enable
"N": No Connect
TCXO
VCTCXO
DCTCXO
Temperature Range
SiT5156AC - FK - 33 E 0 -
19.123456
T
SiT5156AC - FK - 33 V T -
19.123456
T
SiT5156AC - FKG33 J R -
19.123456
T
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
“X”: 12 mm Tape & Reel, 250 u reel
(blank): bulk
[2]
Frequency
1.000000 MHz to 60.000000 MHz
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
Output Waveform
"-": LVCMOS
"C": Clipped Sinewave
[1]
Frequency Stability
"K": for
±0.5
ppm
"A": for
±1.0
ppm
"D": for
±2.5
ppm
Pull Range
–
DCTCXO mode only
"T":
±6.25
ppm
"R":
±10
ppm
"Q":
±12.5
ppm
"M":
±25
ppm
"B":
±50
ppm
"C":
±80
ppm
"E":
±100
ppm
"F":
±125
ppm
"G":
"H":
"X":
"L":
"Y":
"S":
"Z":
"U":
±150 ppm
±200 ppm
±400 ppm
±600 ppm
±800 ppm
±1200 ppm
±1600 ppm
±3200 ppm
I
2
C Address Mode
–
DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I
2
C address. When the I
2
C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I
2
C pin addressable mode. Address is set by
the logic on A0 pin.
Pin 1 Function
–
DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Supply Voltage
"25": 2.5 V
±
10%
"28": 2.8 V
±
10%
"30": 3.0 V
±
10%
"33": 3.3 V
±
10%
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in
Table 1
(Electrical Characteristics). Contact
SiTime
for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact
SiTime.
2. Bulk is available for sampling only
Rev 1.06
Page 2 of 38
www.sitime.com
SiT5156
1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics.............................................................................................................................................................. 4
Device Configurations and Pin-outs ............................................................................................................................................. 9
Pin-out Top Views................................................................................................................................................................. 9
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10
Waveforms................................................................................................................................................................................. 12
Timing Diagrams ........................................................................................................................................................................ 13
Typical Performance Plots ......................................................................................................................................................... 14
Architecture Overview ................................................................................................................................................................ 16
Frequency Stability ............................................................................................................................................................. 16
Output Frequency and Format............................................................................................................................................ 16
Output Frequency Tuning ................................................................................................................................................... 16
Pin 1 Configuration (OE, VC, or NC)
.................................................................................................................................. 17
Device Configurations ................................................................................................................................................................ 17
TCXO Configuration ........................................................................................................................................................... 17
VCTCXO Configuration ...................................................................................................................................................... 18
DCTCXO Configuration ...................................................................................................................................................... 19
VCTCXO-Specific Design Considerations ................................................................................................................................. 20
Linearity .............................................................................................................................................................................. 20
Control Voltage Bandwidth ................................................................................................................................................. 20
FV Characteristic Slope K
V
................................................................................................................................................. 20
Pull Range, Absolute Pull Range ........................................................................................................................................ 21
DCTCXO-Specific Design Considerations ................................................................................................................................. 22
Pull Range and Average Pull Range .................................................................................................................................. 22
Output Frequency ............................................................................................................................................................... 23
I
2
C Control Registers .......................................................................................................................................................... 25
Register Descriptions.......................................................................................................................................................... 25
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW)
............................................................ 25
Register Address: 0x01.
OE Control, Digital Frequency Control Most Significant Word (MSW)
......................................... 26
Register Address: 0x02. DIGITAL PULL RANGE CONTROL
[15]
....................................................................................... 27
Serial Interface Configuration Description .......................................................................................................................... 28
Serial Signal Format ........................................................................................................................................................... 28
Parallel Signal Format ........................................................................................................................................................ 29
Parallel Data Format ........................................................................................................................................................... 29
I
2
C Timing Specification ...................................................................................................................................................... 31
I
2
C Device Address Modes ................................................................................................................................................. 32
Schematic Example ............................................................................................................................................................ 33
Dimensions and Patterns ........................................................................................................................................................... 34
Layout Guidelines ...................................................................................................................................................................... 35
Manufacturing Guidelines .......................................................................................................................................................... 35
Additional Information ................................................................................................................................................................ 36
Revision History ......................................................................................................................................................................... 37
Rev 1.06
Page 3 of 38
www.sitime.com
SiT5156
1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3 V Vdd.
Table 1. Output Characteristics
Parameters
Nominal Output Frequency Range
Operating Temperature Range
Symbol
F_nom
T_use
Min.
1
-20
-40
-40
Frequency Stability over
Temperature
Initial Tolerance
Supply Voltage Sensitivity
F_stab
–
–
–
F_init
F_Vdd
–
–
–
–
Output Load Sensitivity
F_load
–
–
–
Frequency vs. Temperature Slope
ΔF/ΔT
–
–
–
Dynamic Frequency Change during
Temperature Ramp
One-Year Aging
20-Year Aging
F_dynamic
–
–
–
F_1y
F_20y
–
–
Typ.
–
–
–
–
–
–
–
–
±7.10
±11.83
±28.40
±0.81
±1.35
±3.24
±15
±25
±60
±0.13
±0.21
±0.50
±1
±2
Max.
60
+70
+85
+105
±0.5
±1.0
±2.5
±1
±16.25
±32.50
±65.0
±2.75
±5.50
±11.00
±25
±50
±100
±0.21
±0.42
±0.83
–
–
Unit
MHz
°C
°C
°C
ppm
ppm
ppm
ppm
ppb
ppb
ppb
ppb
ppb
ppb
ppb/°C
ppb/°C
ppb/°C
ppb/s
ppb/s
ppb/s
ppm
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
±0.5 ppm F_stab, Vdd ±5%
±1.0ppm F_stab, Vdd ±5%
±2.5 ppm F_stab, Vdd ±5%
±0.5 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped
sinewave output, 10
kΩ
|| 10 pF ±10%
±1.0 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped
sinewave output, 10
kΩ
|| 10 pF ±10%
±2.5 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped
sinewave output, 10
kΩ
|| 10 pF ±10%
±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
Extended Commercial, ambient temperature
Industrial, ambient temperature
Extended Industrial, ambient temperature
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
Condition
Frequency Coverage
Temperature Range
Frequency Stability
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Output Impedance
DC
Tr, Tf
VOH
VOL
Z_out_c
45
0.8
90%
–
–
–
–
–
Output Voltage Swing
Rise/Fall Time
Start-up Time
V_out
Tr, Tf
T_start
0.8
–
–
–
1.2
–
–
17
17
18
19
–
3.5
2.5
55
1.9
–
10%
–
–
–
–
1.2
4.6
3.5
%
ns
Vdd
Vdd
Ohms
Ohms
Ohms
Ohms
V
ns
ms
10% - 90% Vdd
IOH = +3 mA
IOL = -3 mA
Impedance looking into output buffer, Vdd = 3.3 V
Impedance looking into output buffer, Vdd = 3.0 V
Impedance looking into output buffer, Vdd = 2.8 V
Impedance looking into output buffer, Vdd = 2.5 V
Clipped sinewave output, 10
kΩ
|| 10 pF ±10%
20% - 80% Vdd, F = 19.2 MHz
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0V to
Vdd
F_nom = 10 MHz. See
Timing Diagrams
section below.
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value. Vdd
ramp time = 100 µs
Clipped Sinewave Output Characteristics
Start-up Characteristics
Output Enable Time
Time to Rated Frequency Stability
T_oe
T_stability
–
–
–
5
680
45
ns
ms
Rev 1.06
Page 4 of 38
www.sitime.com
SiT5156
1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Table 2. DC Characteristics
Parameters
Supply Voltage
Symbol
Vdd
Min.
2.25
2.52
2.7
2.97
Current Consumption
OE Disable Current
Idd
I_od
–
–
–
–
Typ.
2.5
2.8
3.0
3.3
44
48
43
47
Max.
2.75
3.08
3.3
3.63
53
57
51
55
Unit
V
V
V
V
mA
mA
mA
mA
F_nom = 19.2 MHz, No Load, TCXO and DCTCXO modes
F_nom = 19.2 MHz, No Load, VCTCXO mode
OE = GND, output weakly pulled down. TCXO, DCTCXO
OE = GND, output weakly pulled down. VCTCXO mode
Condition
Contact
SiTime
for 2.25 V to 3.63 V continuous supply
voltage support
Supply Voltage
Current Consumption
Table 3. Input Characteristics
Parameters
Input Impedance
Input High Voltage
Input Low Voltage
Symbol
Z_in
VIH
VIL
Min.
75
70%
–
±6.25
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
±2.75
±2.25
±0.75
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Frequency Control Polarity
Pull Range Linearity
Bus Speed
Input Voltage Low
Input Voltage High
Output Voltage Low
Input Leakage current
Input Capacitance
VC_U
VC_L
VC_z
VC_bw
F_pol
PR_lin
F_I2C
VIL_I2C
VIH_I2C
VOL_I2C
I
L
C
IN
–
70%
–
0.5
–
–
90%
–
8
–
Typ.
–
–
–
–
Max.
–
–
30%
–
Unit
kΩ
Vdd
Vdd
ppm
VCTCXO mode; contact
SiTime
for ±12.5 and ±25 ppm
Internal pull up to Vdd
Condition
Input Characteristics
–
OE Pin
Frequency Tuning Range – Voltage Control or I
2
C mode
Pull Range
PR
–
–
ppm
DCTCXO mode
Absolute Pull Range
[3]
APR
–
–
–
–
–
–
10
Positive
0.5
≤
400
≤ 1000
–
–
–
–
–
–
–
–
–
10%
–
–
1.0
ppm
ppm
ppm
Vdd
Vdd
MΩ
kHz
%
kHz
kHz
±0.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±1.0 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±2.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
VCTCXO mode
VCTCXO mode
VCTCXO mode
VCTCXO mode; contact
SiTime
for other bandwidth options
VCTCXO mode
VCTCXO mode
-40 to 105°C
-40 to 85°C
DCTCXO mode
DCTCXO mode
DCTCXO mode
0.1 V
DD
< VOUT < 0.9 V
DD.
Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
DCTCXO mode
I
2
C Interface Characteristics, 200 Ohm, 550 pF (Max I
2
C Bus Load)
30%
–
0.4
24
5
Vdd
Vdd
V
µA
pF
Note:
3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to
Table 17
for APR with respect to other pull range options.
Rev 1.06
Page 5 of 38
www.sitime.com
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