SiT9005
1 to 141 MHz EMI Reduction Oscillator
Features
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Applications
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Spread spectrum for EMI reduction
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Wide spread % option
Center spread: from ±0.125% to ±2%, ±0.125%
step size
Down spread: -0.25% to -4% with -0.25%
step size
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Spread profile option: Triangular, Hershey-kiss
Programmable rise/fall time for EMI reduction:
8 options, 0.25 to 40 ns
Any frequency between 1 MHz and 141 MHz accurate to
6 decimal places
100% pin-to-pin drop-in replacement to quartz-based XO’s
Excellent total frequency stability as low as ±20 ppm
Operating temperature from -40°C to 85°C
Low power consumption of 4.0 mA typical at 1.8 V
Pin1 modes: Standby, output enable, or spread disable
Fast startup time of 5 ms
LVCMOS output
Industry-standard packages
▪
QFN: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5 mm
2
▪
Contact SiTime
for SOT23-5 (2.9 x 2.8 mm
2
)
RoHS and REACH compliant, Pb-free, Halogen-free
and Antimony-free
Surveillance camera
IP camera
Industrial motors
Flat panels
Multi function printers
PCI express
Electrical Specifications
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated.
Typical values are at 25°C and 3.3 V supply voltage.
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-20
-25
-50
Operating Temperature Range
T_use
-20
-40
Supply Voltage
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
OE Disable Current
Idd
I_OD
–
–
–
–
Standby Current
I_std
–
–
Typ.
–
–
–
–
–
–
1.8
2.5
2.8
3.0
3.3
–
5.6
5.0
5.0
4.6
2.1
0.4
Max.
141
+20
+25
+50
+70
+85
1.98
2.75
3.08
3.3
3.63
3.63
6.5
5.5
6.5
5.2
4.3
1.5
Unit
MHz
ppm
ppm
ppm
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
A
A
No load condition, f = 40 MHz, Vdd = 2.5 V to 3.3 V
No load condition, f = 40 MHz, Vdd = 1.8 V
f = 40 MHz, Vdd = 2.5 V to 3.3 V, OE = GND, Output in
high-Z state
f = 40 MHz, Vdd = 1.8 V, OE = GND, Output in high-Z state
Extended Commercial
Industrial
Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage. Spread = Off.
Condition
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Supply Voltage and Current Consumption
ST
= GND, Vdd = 2.5 V to 3.3 V, Output is weakly pulled down
ST
= GND, Vdd = 1.8 V, Output is weakly pulled down
Rev 1.01
11 March 2021
www.sitime.com
SiT9005
1 to 141 MHz EMI Reduction Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Duty Cycle
Rise/Fall Time
Symbol
DC
Tr, Tf
Min.
45
–
–
–
Output High Voltage
VOH
90%
Typ.
–
1
1.3
–
–
Max.
55
2
2.5
2
–
Unit
%
ns
ns
ns
Vdd
Vdd = 2.5 V, 2.8 V, 3.0 V or 3.3 V, 20% - 80%, default derive
strength
Vdd =1.8 V, 20% - 80%, default derive strength
Vdd = 2.25 V - 3.63 V, 20% - 80%, default derive strength
IOH = -4 mA (Vdd = 3.0 V or 3.3 V)
IOH = -3 mA (Vdd = 2.8 V and Vdd = 2.5 V)
IOH = -2 mA (Vdd = 1.8 V)
IOL = 4 mA (Vdd = 3.0 V or 3.3 V)
IOL = 3 mA (Vdd = 2.8 V and Vdd = 2.5 V)
IOL = 2 mA (Vdd = 1.8 V)
Pin 1, OE or ST
̅ ̅̅
Pin 1, OE or ST
̅ ̅̅
Pin 1, OE logic high or logic low, or ST logic high
̅ ̅̅
Pin 1, ST logic low
̅ ̅̅
Measured from the time Vdd reaches its rated minimum value
f = 40 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Measured from the time ST pin crosses 50% threshold
Measured from the time SD pin crosses 50% threshold
Measured from the time SD pin crosses 50% threshold
f = 40 MHz, Vdd = 2.5 to 3.3V, Spread = ON( or OFF)
f = 40 MHz, Vdd = 3.3V, Spread = ON( or OFF)
f = 40 MHz, Vdd = 1.8V, Spread = ON( or OFF)
Condition
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
VIH
VIL
Z_in
70%
–
50
2
Startup Time
Enable/Disable Time
Resume Time
Spread Enable Time
Spread Disable Time
Cycle-to-cycle jitter
T_start
T_oe
T_resume
T_sde
T_sdde
T_ccj
–
–
–
–
–
–
–
–
–
–
87
–
–
–
–
–
–
10.5
8.5
12.5
–
30%
150
–
5
180
5
4
50
Jitter
15
12
22
ps
ps
ps
Vdd
Vdd
k
M
ms
ns
ms
µs
µs
Startup and Resume Timing
Table 2. Spread Spectrum %
[1,2]
Ordering
Code
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Center Spread
(%)
±0.125
±0.250
±0.390
±0.515
±0.640
±0.765
±0.905
±1.030
±1.155
±1.280
±1.420
±1.545
±1.670
±1.795
±1.935
±2.060
Down Spread
(%)
-0.25
-0.50
-0.78
-1.04
-1.29
-1.55
-1.84
-2.10
-2.36
-2.62
-2.91
-3.18
-3.45
-3.71
-4.01
-4.28
Table 3. Spread Profile
Spread Profile
Triangular
Hershey-kiss
Notes:
1. In both center spread and down spread modes, modulation rate is
employed with a frequency of ~31.25 kHz.
2.
Contact SiTime
for wider spread options
Rev 1.01
Page 2 of 10
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SiT9005
1 to 141 MHz EMI Reduction Oscillator
Table 4. Pin Description
Pin
1
Symbol
OE /
ST
/
NC / SD
Output
Enable
Standby
[3]
Functionality
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
H
[3]
: specified frequency output
L: output is low (week pull down). Device goes to sleep mode.
Supply current reduced to I_std.
Pin1 has no function (Any voltage between 0 and Vdd or Open)
H: Spread = ON
L: Spread = OFF
Electrical ground
Oscillator output
Power supply voltage
[4]
GND
OE/
ST
/
̅ ̅̅
NC/SD
Top View
1
4
VDD
No
Connect
Spread
Disable
2
3
4
Notes:
GND
OUT
VDD
Power
Output
Power
2
3
OUT
Figure 1. Pin Assignments
3. In OE or
ST
mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
4. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Table 5. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[5]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
5. Exceeding this temperature for extended period of time may damage the device.
Table 6. Maximum Operating Junction Temperature
[6]
Max Operating Temperature (ambient)
70°C
85°C
Maximum Operating Junction Temperature
80°C
95°C
Note:
6. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 7. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev 1.01
Page 3 of 10
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SiT9005
1 to 141 MHz EMI Reduction Oscillator
Timing Diagrams
Vdd
50% Vdd
T_resume
90% Vdd
Vdd
T_start
[7]
No Glitch
during start up
Pin 4 Voltage
ST Voltage
CLK Output
CLK Output
HZ
T_start: Time to start from power-off
HZ
T_resume: Time to resume from ST
Figure 2. Startup Timing
Figure 3. Standby Resume Timing
(ST Mode Only)
Vdd
50% Vdd
OE Voltage
T_oe
OE Voltage
Vdd
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to re-enable the clock output
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 4. OE Enable Timing (OE Mode Only)
Figure 5. OE Disable Timing (OE Mode Only)
Vdd
50% Vdd
SD Voltage
T_sde
SD Voltage
Vdd
50% Vdd
Frequency
Deviation (%)
T_sdde
Modulation period = 32µs (31.25kHz)
Time (s)
Frequency
Deviation (%)
Time (s)
Figure 6. SD Enable Timing (SD Mode Only)
Note:
7. SiT9005 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 7. SD Diable Timing (SD Mode Only)
Rev 1.01
Page 4 of 10
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SiT9005
1 to 141 MHz EMI Reduction Oscillator
Programmable Drive Strength
The SiT9005 includes a programmable drive strength
feature to provide a simple, flexible tool to optimize the
clock rise/fall time for specific applications. Benefits from the
programmable drive strength feature are:
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High Output Load Capability
The rise/fall time of the input clock varies as a function of
the actual capacitive load the clock drives. At any given
drive strength, the rise/fall time becomes slower as the
output load increases. As an example, for a 3.3V SiT9005
device with default drive strength setting, the typical rise/fall
time is 1.1 ns for 15 pF output load. The typical rise/fall time
slows down to 2.9 ns when the output load increases to
45 pF. One can choose to speed up the rise/fall time to
1.9 ns by then increasing the drive strength setting on
the SiT9005.
The SiT9005 can support up to 60 pF or higher in
maximum capacitive loads with up to 3 additional drive
strength settings. Refer to
Table 8
through
Table 12
to
determine the proper drive strength for the desired
combination of output load vs. rise/fall time
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Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time
Improves the downstream clock receiver’s (RX) jitter by
decreasing (speeding up) the clock rise/fall time.
Ability to drive large capacitive loads while maintaining
full swing with sharp edge rates.
For more detailed information about rise/fall time control
and drive strength selection, see the
SiTime Application
Notes section.
EMI Reduction by Slowing Rise/Fall Time
Figure 8 shows the harmonic power reduction as the
rise/fall times are increased (slowed down). The rise/fall
times are expressed as a ratio of the clock period. For the
ratio of 0.05, the signal is very close to a square wave. For
the ratio of 0.45, the rise/fall times are very close to near-
triangular waveform. These results, for example, show that
the 11th clock harmonic can be reduced by 35 dB if the
rise/fall edge is increased from 5% of the period to 45% of
the period.
10
0
trise=0.05
trise=0.1
trise=0.15
trise=0.2
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
SiT9005 Drive Strength Selection
Table 8 through Table 12 define the rise/fall time for a given
capacitive load and supply voltage.
Select the table that matches the SiT9005 nominal
supply voltage (1.8 V, 2.5 V, 2.8 V, 3.3 V).
Select the capacitive load column that matches the
application requirement (15 pF to 60 pF)
Under the capacitive load column, select the desired
rise/fall times.
The left-most column represents the part number
code for the corresponding drive strength.
Add the drive strength code to the part number for
ordering purposes.
Harmonic amplitude (dB)
-10
-20
-30
-40
-50
-60
-70
-80
1
3
5
7
9
Calculating Maximum Frequency
Based on the rise and fall time data given in
Table 8
through
Table 12,
the maximum frequency the oscillator
can operate with guaranteed full swing of the output voltage
over temperature as follows:
Max Frequency =
11
1
5 x Trf_20/80
Harmonic number
Figure 8. Harmonic EMI reduction as a Function
of Slower Rise/Fall Time
where Trf_20/80 is the typical rise/fall time at 20% to 80%
Vdd
Example 1
Calculate f
MAX
for the following condition:
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Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to
increase rise/fall time (edge rate) of the input clock. Some
chipsets would require faster rise/fall time in order to
reduce their sensitivity to this type of jitter. The SiT9005
provides up to 3 additional high drive strength settings for
very fast rise/fall time. Refer to
Table 8
through
Table 12
to
determine the proper drive strength.
Vdd = 3.3 V (Table
12)
Capacitive Load: 30 pF
Desired Tr/f time = 1.6 ns
(rise/fall time part number code = Z)
Part number for the above example:
SiT9005AIZ14-33EB-105.12345
Drive strength code is inserted here. Default setting is “-”
Rev 1.01
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