SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
31 standard frequencies from 25 MHz to 212.5 MHz
LVPECL and LVDS output signaling types
0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±10 ppm
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2x2.5, 5.0x3.2 and 7.0x5.0 mmxmm
For any other frequencies between 1 to 625 MHz, refer to SiT9121
and SiT9122 datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Telecom, networking, instrumentation, storage, servers
Electrical Characteristics
Parameter and Conditions
Supply Voltage
Symbol
Vdd
Min.
2.97
2.25
2.25
Output Frequency Range
Frequency Stability
f
F_stab
25
-10
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Start-up Time
Resume Time
Duty Cycle
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
F_aging1
F_aging10
T_use
VIH
VIL
Z_in
T_start
T_resume
DC
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
-2
-5
-40
-20
70%
–
–
2
–
–
45
–
–
–
–
–
Vdd-1.1
Vdd-1.9
1.2
–
–
–
–
–
–
Typ.
3.3
2.5
–
–
–
–
–
–
–
–
–
–
–
–
100
–
6
6
–
61
–
–
–
–
–
–
1.6
300
–
1.2
1.2
1.2
0.6
Max.
3.63
2.75
3.63
212.5
+10
+20
+25
+50
+2
+5
+85
+70
–
30%
250
–
10
10
55
69
35
1
100
30
Vdd-0.7
Vdd-1.5
2.0
500
115
1.7
1.7
1.7
0.85
Unit
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
kΩ
MΩ
ms
ms
%
mA
mA
A
A
mA
V
V
V
ps
ns
ps
ps
ps
ps
25°C
25°C
Industrial
Extended Commercial
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time ST pin crosses
50% threshold.
Contact SiTime for tighter duty cycle
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
See Figure 2
Termination schemes in Figures 1 and 2 - XX ordering code
See last page for list of standard frequencies
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
Condition
LVPECL and LVDS, Common Electrical Characteristics
LVPECL, DC and AC Characteristics
RMS Phase Jitter (random)
T_phj
LVDS, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Idd
I_OE
VOD
–
–
250
47
–
350
55
35
450
mA
mA
mV
SiTime Corporation
Rev. 1.06
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised October 3, 2014
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
(continued)
Parameter and Conditions
Output Disable Leakage Current
Standby Current
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Symbol
I_leak
I_std
VOD
VOS
VOS
Tr, Tf
T_oe
T_jitt
Min.
–
–
–
1.125
–
–
–
–
–
–
–
Typ.
–
–
–
1.2
–
495
–
1.2
1.2
1.2
0.6
Max.
1
100
50
1.375
50
600
115
1.7
1.7
1.7
0.85
Unit
A
A
mV
V
mV
ps
ns
ps
ps
ps
ps
OE = Low
ST = Low, for all Vdds
See Figure 2
See Figure 2
See Figure 2
20% to 80%, see Figure 2
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
LVDS, DC and AC Characteristics (continued)
RMS Phase Jitter (random)
T_phj
Pin Description
Pin
Map
OE
1
ST
2
3
4
5
6
NC
GND
OUT+
OUT-
VDD
Input
NA
Power
Output
Output
Power
Input
Functionality
H or Open: specified frequency output
L: output is high impedance
H or Open: specified frequency output
L: Device goes to sleep mode. Supply current reduces to
I_std.
No Connect; Leave it floating or connect to GND for better
heat dissipation
VDD Power Supply Ground
Oscillator output
Complementary oscillator output
Power supply voltage
Top View
OE/ST
1
NC
2
GND
3
6
VDD
OUT-
OUT+
5
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge (HBM)
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050, 6-pin
5032, 6-pin
3225, 6-pin
JA, 4 Layer Board
(°C/W)
142
97
109
JC, Bottom
(°C/W)
27
20
20
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.06
Page 2 of 8
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SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice
The Smart Timing Choice
Waveform Diagrams
OUT-
80%
80%
20%
OUT+
20%
VOH
Tr
GND
Tf
VOL
Figure 1(a). LVPECL Voltage Levels per Differential Pin (OUT+/OUT-)
V _ S w in g
0 V
t
Figure 1(b). LVPECL Voltage Levels Across Differential Pair
OUT-
80%
VOD
20%
OUT+
20%
VOS
Tr
GND
80%
Tf
Figure 2. LVDS Voltage Levels per Differential Pin (OUT+/OUT-)
Rev. 1.06
Page 3 of 8
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice
The Smart Timing Choice
Termination Diagrams
LVPECL:
VDD
OUT+
L V P E C L D rive r
OUT-
Z0 = 5 0
50
50
Z 0 = 50
D+
Receiver Device
D-
V T T = V D D – 2.0 V
Figure 3. LVPECL Typical Termination
VDD
OUT+
LVPECL Driver
VDD= 3.3V => R1 = 100 to 150
VDD= 2.5V => R1 = 75
100 nF
D+
Receiver Device
100 nF
Z0 = 50
OUT-
R1
R1
Z0 = 50
50
50
D-
VTT
Figure 4. LVPECL AC Coupled Termination
VDD = 3.3V => R1 = R3 = 133
and
R2 = R4 = 82
VDD = 2.5V => R1 = R3 = 250
and
R2 = R4 = 62.5
VDD
OUT+
LVPECL Driver
OUT-
Z0 = 50
R2
R4
Z0 = 50
VDD
R1
R3
D+
Receiver Device
D-
Figure 5. LVPECL with Thevenin Typical Termination
Rev. 1.06
Page 4 of 8
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice
The Smart Timing Choice
LVDS:
VDD
OUT+
LVDS Driver
OUT-
Z0 = 50
100
Z0 = 50
D+
Receiver Device
D-
Figure 6. LVDS Single Termination (Load Terminated)
Rev. 1.06
Page 5 of 8
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