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SIT9501AE-01B2-1810-50.000000

LVPECL Output Clock Oscillator, 50MHz Nom,

器件类别:无源元件    振荡器   

厂商名称:SiTime

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器件参数
参数名称
属性值
Objectid
145225467652
Reach Compliance Code
compliant
Country Of Origin
Malaysia, Taiwan, Thailand
YTEOL
6.71
其他特性
ENABLE/DISABLE FUNCTION
频率调整-机械
NO
频率稳定性
25%
安装特点
SURFACE MOUNT
端子数量
6
标称工作频率
50 MHz
最高工作温度
105 °C
最低工作温度
-40 °C
振荡器类型
LVPECL
输出负载
15 pF
封装等效代码
SOLCC6,.1,43
物理尺寸
3.2mm x 2.5mm x 0.9mm
最大供电电压
3.63 V
最小供电电压
1.71 V
标称供电电压
1.8 V
表面贴装
YES
最大对称度
55/45 %
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SiT9501
ADVANCED
Ultra-low Jitter Differential XO for Standard Networking Frequencies
Description
The SiT9501 is a differential MEMS oscillator that is
engineered for low-jitter applications requiring standard
networking frequencies from 25 MHz to 644.53125 MHz.
A unique FlexSwing output-driver performs like LVPECL
but provides independent control of voltage swing and DC
offset to simplify interfacing with chipsets having non-
standard input voltage requirements and eliminate all
external source-bias resistors. The device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for an external dedicated LDO.
The SiT9501 can be factory programmed for specific
combinations of frequency, stability, voltage, output
signaling, and pin 1 functionality. Programmability enables
designers to optimize clock configurations while
eliminating long lead times and customization costs
associated with quartz devices where each combination is
custom built.
The wide frequency range and programmability makes
this device ideal for communications, enterprise, and
industrial applications that require a variety of frequencies
and operate in noisy environments.
Refer to
Manufacturing Notes
for proper reflow profile,
tape and reel dimension, and other manufacturing related
information.
Features
14 Standard networking frequencies from 25 MHz to
644.53125 MHz
70 fs RMS typical phase jitter, 12 kHz to 20 MHz
Excellent power-supply noise rejection
LVPECL, LVDS, HCSL, Low-power HCSL, and
FlexSwing signaling options
±20, ±25, ±30, and ±50 ppm frequency stabilities
Wide temperature support up to -40°C to 105°C
Factory programmable options for low lead time
1.8 V, 2.5 V, 3.3 V, and wide continuous range power
supply voltage
2 x 1.6, 2.5 x 2, 3.2 x 2.5 mm x mm package
(Contact
SiTime
for 7 x 5, and 5 x 3.2 mm x mm
packages)
Applications
400G/800G network equipment
Optical modules
Coherent optics
Network switches, routers
Industrial networking equipment
Block Diagram
Package Pinout
OE/NF
NF
GND
1
6
VDD
OUTN
OUTP
2
5
3
4
Figure 1. SiT9501 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 17
for Pin Descriptions)
Rev 0.54
September 23, 2020
www.sitime.com
SiT9501
Ultra-low Jitter Differential XO for Standard Networking Frequencies
Typical Phase Jitter (70 fs RMS) and Phase Noise Data
Table 1. Phase Noise for 3.3 V 156.25 MHz LVPECL Device at 25°C
Offset Frequency (Hz)
100
1k
10k
100k
1M
10M
40M
ADVANCED
Phase Noise (dBc/Hz)
-87
-114
-141
-151
-152
-165
-170
Figure 3. Phase Noise Plot of 3.3 V 156.25 MHz LVPECL Device at 25°C
Rev 0.54
Page 2 of 25
www.sitime.com
SiT9501
Ultra-low Jitter Differential XO for Standard Networking Frequencies
Ordering Information
ADVANCED
SiT9501AC-01B2-3310-125.000000T
Part Family
“SiT9501”
Revision Letter
“A” is the revision of Silicon
Temperature Range
“C”:
“I”:
“B”:
“E”:
Extended Commercial, -20 to 70°C
Industrial, -40 to 85°C
-40 to 95°C
Extended Industrial, -40 to 105°C
Frequency
“25.000000”: 25.000000 MHz
“39.062500”: 39.062500 MHz
“50.000000”: 50.000000 MHz
“53.125000”: 53.125000 MHz
“62.500000”: 62.500000 MHz
“78.125000”: 78.125000 MHz
“125.000000”: 125.000000 MHz
“156.250000”: 156.250000 MHz
“161.132813”: 161.132813 MHz
“250.000000”: 250.000000 MHz
“312.500000”: 312.500000 MHz
“322.265625”: 322.265625 MHz
“625.000000”: 625.000000 MHz
“644.531250”: 644.531250 MHz
Reserved
“0-”: Default
Pin 1 Functionality
“0”: NF (no function)
“1”: OE active high
“2”: OE active low
Supply Voltage
“18”: 1.8 V ±5%
“25”: 2.5 V ±10%
“33”: 3.3 V ±10%
“XX”: 2.25 V to 3.63 V
“YY”: 1.71 V to 3.63 V
Packaging
Refer to
Table 2
for packing method
Leave blank for bulk (for sampling only)
Signaling Group
“-”: LVPECL, LVDS, HCSL, Low-power
HCSL
“1”: FlexSwing referenced to voltage
on VDD pin.
For FlexSwing referenced to voltage
on GND pin,
Contact SiTime.
Signaling Type
“01”: LVPECL
“02”: LVDS
“04”: HCSL
“08”: Low-power HCSL, with integrated
series termination
“FS”, “WB”, “EP”: FlexSwing, see
Table 5
for VHn and VLn.
Contact SiTime
for other options.
Package Size
“P”: 2.0 x 1.6 mm x mm
“A”: 2.5 x 2.0 mm x mm
“B”: 3.2 x 2.5 mm x mm
Frequency Stability
“1”:
“2”:
“8”:
“3”:
±20 ppm
±25 ppm
±30 ppm
±50 ppm
Table 2. Ordering Codes for Supported Tape & Reel Packing Method
Device Size
(mm x mm)
2.0 x 1.6
2.5 x 2.0
3.2 x 2.5
8 mm T&R
(3ku)
D
D
D
8 mm T&R
(1ku)
E
E
E
8 mm T&R
(250u)
G
G
G
Rev 0.54
Page 3 of 25
www.sitime.com
SiT9501
Ultra-low Jitter Differential XO for Standard Networking Frequencies
TABLE OF CONTENTS
ADVANCED
Description ................................................................................................................................................................................... 1
Features ....................................................................................................................................................................................... 1
Applications .................................................................................................................................................................................. 1
Block Diagram .............................................................................................................................................................................. 1
Package Pinout ............................................................................................................................................................................ 1
Typical Phase Jitter (70 fs RMS) and Phase Noise Data ............................................................................................................. 2
Ordering Information .................................................................................................................................................................... 3
Electrical Characteristics .............................................................................................................................................................. 5
Pin Description ........................................................................................................................................................................... 13
FlexSwing Configurations ........................................................................................................................................................... 14
Waveform Diagrams................................................................................................................................................................... 16
Termination Diagrams ................................................................................................................................................................ 19
LVPECL and FlexSwing Termination .................................................................................................................................. 19
LVDS, Supply Voltage: 1.8 V
±5%,
2.5 V ±10%, 3.3 V ±10%, 2.25 V to 3.63 V, 1.71 V to 3.63 V ...................................... 20
HCSL, Supply Voltage: 1.8 V
±5%,
2.5 V ±10%, 3.3 V ±10%, 2.25 V to 3.63 V, 1.71 V to 3.63 V ...................................... 20
Low-power HCSL, Supply Voltage: 1.8 V
±5%,
2.5 V ±10%, 3.3 V ±10%, 2.25 V to 3.63 V, 1.71 V to 3.63 V .................... 20
Dimensions and Patterns ― 2.0 x 1.6 mm x mm ....................................................................................................................... 21
Dimensions and Patterns ― 2.5 x 2.0 mm x mm ....................................................................................................................... 22
Dimensions and Patterns ― 3.2 x 2.5 mm x mm ....................................................................................................................... 23
Additional Information................................................................................................................................................................. 24
Revision History ......................................................................................................................................................................... 24
Rev 0.54
Page 4 of 25
www.sitime.com
SiT9501
Ultra-low Jitter Differential XO for Standard Networking Frequencies
Electrical Characteristics
ADVANCED
All Min and Max limits in the Electrical Characteristics tables are specified over operating temperature and rated operating
voltage with standard output termination shown in the termination diagrams. Typical values are at 25°C and nominal
supply voltage.
Table 3. Electrical Characteristics – Common to All Output Signaling Types
Parameter
Output Frequency Range
Symbol
f
Min.
Typ.
Max.
Unit
MHz
Condition
Refer to frequencies listed in
Error! Not a valid result for table.
s
ection.
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, load variation of 15 pF
±
10%, and 10 years
aging at 25°C
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, load variation of 15 pF
±
10%, and first year aging
at 25°C
Ambient temperature of 25°C
Extended commercial, ambient temperature
Industrial, ambient temperature
Ambient temperature
Extended industrial, ambient temperature
Voltage-supply order code “YY”
Voltage-supply order code “XX”
Voltage-supply order code “18”.
Contact SiTime
for 1.5 V
Voltage-supply order code “25”
Voltage-supply order code “33”
Pins 1 and 2 for OE and SE, respectively
Pins 1 and 2 for OE and SE, respectively
Pins 1 and 2 for OE and SE, respectively
See
Figure 6
and
Figure 8
Measured from the time Vdd reaches its rated minimum value
Measured from the time OE pin toggles to enable logic level to
the time clock pins reach 90% of swing. See
Figure 13
Measured from the time OE pin toggles to disable logic level to
the last clock edge. See
Figure 14
12 kHz to 20 MHz offset frequency integration bandwidth
12 kHz to 20 MHz offset frequency range
Frequency Range
Standard frequencies
Frequency Stability
Frequency Stability
F_stab
±20
ppm
10 Year Aging
Operating Temperature Range
F_10y
T_use
-20
-40
-40
-40
Supply Voltage
Vdd
1.71
2.25
1.71
2.25
2.97
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Duty Cycle
Startup Time
Output Enable Time
Output Disable Time
VIH
VIL
Z_in
DC
T_start
T_oe
T_od
70%
45
±1
1.80
2.50
3.30
100
1
±25
±30
±50
+70
+85
+95
+105
ppm
ppm
ppm
ppm
°C
°C
°C
°C
V
V
V
V
V
Temperature Range
Supply Voltage
3.63
3.63
1.89
2.75
3.63
Input Characteristics
Vdd
30%
55
5
100+3 clock
cycles
100+3 clock
cycles
100
Vdd
%
ms
ns
ns
Output Characteristics
Startup, OE and SE Timing
Jitter and Phase Noise, f = 156.25 MHz
RMS Phase Jitter (random)
Spurious Phase Noise
RMS Period Jitter
[1]
[1]
T_phj
T_spn
T_jitt_per
T_jitt_cc
70
-110
1
6
fs
dBc
ps
ps
Peak Cycle-to-cycle Jitter
Note:
1. Measured according to JESD65B.
Rev 0.54
Page 5 of 25
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